NCV887601D1R2G

DATA SHEET www.onsemi.com Automotive Grade Start-Stop Non-Synchronous Boost Controller 8 1 SOIC−8 D SUFFIX CASE 751 NCV8876 The NCV8876 is a Non-Synchronous Boost controller designed to supply a minimum output voltage during Start-Stop vehicle operation battery voltage sags. The controller drives an external N-channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include, cycle-by-cycle current limiting, protection and thermal shutdown. Additional features include low quiescent current sleep mode operation. The NCV8876 is enabled when the supply voltage drops below 7.3 V, with boost operation initiated when the supply voltage is below 6.8 V. Features • • • • • • • • • • • • Automatic Enable Below 7.3 V (Factory Programmable) Boost Mode Operation at 6.8 V $2% Output Accuracy Over Temperature Range Peak Current Mode Control with Internal Slope Compensation Externally Adjustable Frequency Operation Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump Low Quiescent Current in Sleep Mode ( Tsd to stop switching − − 100 ns NCV887601 6.66 6.8 6.94 V VOLTAGE REGULATION Voltage Regulation VOUT,reg Threshold IC Enable VOUT descending NCV887601 7.1 7.3 7.5 V Threshold IC Disable VOUT ascending NCV887601 7.5 7.7 7.9 V Threshold IC Enable – Voltage Regulation NCV887601 0.32 0.5 − Threshold IC Disable – Threshold IC Enable NCV887601 − 0.4 − V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Not tested in production. Limits are guaranteed by design. 3. An RGND = 15 kW GDRV−GND resistor is strongly recommended. www.onsemi.com 5 NCV8876 TYPICAL CHARACTERISTICS 2.30 VOUT = 13.2 V Iq,on, QUIESCENT CURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) 22 20 18 16 14 12 10 −50 0 50 100 2.24 2.22 2.20 2.18 2.16 2.14 2.12 100 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Quiescent Current vs. Temperature 150 1.010 117 116 115 114 113 112 111 110 0 50 100 1.005 1.000 0.995 0.990 −50 150 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Normalized Current vs. Temperature Figure 5. Minimum On Time vs. Temperature 169.0 SWITCHING FREQUENCY (kHz) 6.84 6.83 VOUT REGULATION 50 TJ, JUNCTION TEMPERATURE (°C) 118 6.82 6.81 6.80 6.79 6.78 −50 0 Figure 3. Sleep Current vs. Temperature NORMALIZED CURRENT LIMIT Ton,min, MINIMUM ON TIME (ns) 2.26 2.10 −50 150 119 109 −50 VOUT = 13.2 V fs = 170 kHz 2.28 0 50 168.8 168.6 168.4 168.2 168.0 167.8 167.6 167.4 167.2 167.0 150 −50 100 ROSC = Open 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 8. Switching Frequency vs. Temperature Figure 7. VOUT Regulation vs. Temperature www.onsemi.com 6 150 NCV8876 4.1 7.8 THRESHOLD IC VOLTAGE (V) VOUT Rising UVLO THRESHOLD (V) 4.0 3.9 3.8 3.7 VOUT Falling 3.6 3.5 −50 0 50 100 ENABLE 7.7 7.6 7.5 7.4 DISABLE 7.3 7.2 −50 150 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. UVLO Threshold vs. Temperature Figure 10. Threshold IC Voltage vs. Temperature 150 THEORY OF OPERATION L ROSC ROSC Oscillator PWM Comparator GDRV S Q Gate Drive R NRVB440FS VOUT NVMFS5844NL CO RGDRV ISNS + VIN RL RSNS CSA Slope Compensation Voltage Error WAKEUP VOUT VEA VMICRO NCV8876 STATUS STATUS Compensation Figure 11. Current Mode Control Schematic Regulation beyond the ascending voltage threshold (7.7 V for the NCV887600). The NCV8876 VOUT pin serves the dual purpose: (1) powering the NCV8876 and (2) providing the regulation feedback signal. The feedback network is imbedded within the IC to eliminate the constant current battery drain that would exist with the use of external voltage feedback resistors. There is no soft−start operating mode. The NCV8876 will instantly respond to a voltage sag so as to maintain normal operation of downstream loads. Once the NCV8876 is enabled, the voltage error operational transconductance amplifier supplies current to set VC to 1.1 V to minimize the feedback loop response time when the battery voltage sag goes below the regulation set point. The NCV8876 is a non−synchronous boost controller designed to supply a minimum output voltage during Start−Stop vehicle operation battery voltage sags. The NCV8876 is in low quiescent current sleep mode under normal battery operation (12 V) and is enabled when the supply voltage drops below the descending threshold (7.3 V for the NCV887601). Boost operation is initiated when the supply voltage is below the regulation set point (6.8 V for the NCV887601). Once the supply voltage sag condition ends and begins to increase, the NCV8876 boost operation will cease when the supply voltage increases beyond the regulation set point. The NCV8876 low quiescent current sleep mode resumes once the supply voltage increases www.onsemi.com 7 NCV8876 Current Mode Control power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. If the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. The device will remain off for the hiccup time of duration 1024/fosc. The NCV8876 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8876 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. UVLO Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. VDRV An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to ensure fast turn on times. The capacitor should be between 0.1 mF and 1 mF, depending on switching speed and charge requirements of the external MOSFET. VDRV uses an internal linear regulator to charge the VDRV bypass capacitor. VOUT must be decoupled at the IC by a capacitor that is equal or larger in value than the VDRV decoupling capacitor. Current Limit The NCV8876 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the GDRV An RGND = 15 kW GDRV−GND resistor is strongly recommended. APPLICATION INFORMATION Design Methodology IOUT(max): maximum output current [A] ICL: desired typical cycle-by-cycle current limit [A] This section details an overview of the component selection process for the NCV8876 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Operating Frequency 3. Select Current Sense Resistor 4. Select Output Inductor 5. Select Output Capacitors 6. Select Input Capacitors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode 10. Design Notes 11. Determine Feedback Loop Compensation Network From this the ideal minimum and maximum duty cycles can be calculated as follows: D min + 1 * D max + 1 * V IN(max) V OUT V IN(min) V OUT Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated Dmax is higher the Dmax of the NCV8876, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ration of a boost converter goes up to infinity as 1. Define Operational Parameters Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] www.onsemi.com 8 NCV8876 D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will skip pulses at high VIN: Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] 4. Select Output Inductor The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VOUT. After choosing a peak current ripple value, calculate the inductor value as follows: D min w t on(min) fs Where: fs: switching frequency [Hz] ton(min): minimum on time [s] 2. Select Operating Frequency The default setting is an open ROSC pin, allowing the oscillator to operate at the default frequency Fs. Adding a resistor to GND increases the switching frequency. The graph in Figure 12, below, shows the required resistance to program the frequency. From 200 kHz to 500 kHz, the following formula is accurate to within 3% of the expected. L+ 90 80 ROSC (kW) 70 60 I L,AVG + 50 40 V OUTI OUT(max) V IN(min)h The Peak Inductor current can be calculated as follows: 30 I L,peak + I L,avg ) 20 10 150 DI L,max f s Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] The maximum average inductor current can be calculated as follows: 100 0 V IN(WC) D WC DI L,max 2 Where: IL,peak: Peak inductor current value [A] 200 250 300 350 400 FSW (kHz) 450 500 550 5. Select Output Capacitors The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: Figure 12. ROSC vs. FSW R OSC + 2859 (F sw * 170) V OUT(ripple) + Where: fsw: switching frequency [kHz] ROSC: resistor from ROSC pin to GND [k] Note: The ROSC resistor ground return to the NCV8876 pin 3 must be independent of power grounds. DI OUT(max) fC OUT ǒ I OUT(max) 1*D ) V IN(min)D 2fL Ǔ R ESR The capacitors need to survive an RMS ripple current as follows: 3. Select Current Sense Resistor Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + ) I Cout(RMS) + I OUT Ǹ D WC D ) WC 12 DȀ WC ǒ DȀ WC L R OUT T SW Ǔ 2 The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. V CL I CL www.onsemi.com 9 NCV8876 6. Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. I Cin(RMS) + • V IN(WC) 2 D WC Lf sV OUT2 Ǹ3 7. Select Compensator Components Current Mode control method employed by the NCV8876 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. • 8. Select MOSFET(s) • In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: Q g(total) v • I drv fs Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: I Q(max) + I out • ǸD DȀ The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: • V Q(max) + V OUT(max) NVMFS5844NL 12 mW, 60 V SO−8FL package MOSFET is a recommended device. develop at IC pin VOUT which could affect performance. ♦ Use a 1 mF IC VOUT pin decoupling capacitor close to IC in addition to the VDRV decoupling capacitor. Classic feedback loop measurements are not possible (VOUT pin serves a dual purpose as a feedback path and IC power). Feedback loop computer modeling recommended. ♦ A step load test for stability verification is recommended. Compensation ground must be dedicated and connected directly to IC ground. ♦ Do not use vias. Use a dedicated ground trace. ROSC programming resistor ground must be dedicated and connected directly to IC ground ♦ Do not use vias. Use a dedicated ground trace. IC ground & current sense resistor ground sense point must be located on the same side of PCB. ♦ Vias introduce sufficient ESR/ESL voltage drop which can degrade the accuracy of the current feedback signal amplitude (signal bounce) and should be avoided. Star ground should be located at IC ground pad. ♦ This is the location for connecting the compensation and current sense grounds. The IC architecture has a leading edge ISNS blanking circuit. In some instances, current pulse leading edge current spike RC filter may be required. ♦ If required, 120 pF + 750 W are a recommended evaluation starting point. 11. Determine Feedback Loop Compensation Network The purpose of a compensation network is to stabilize the dynamic response of the converter. By optimizing the compensation network, stable regulation response is achieved for input line and load transients. Compensator design involves the placement of poles and zeros in the closed loop transfer function. Losses from the boost inductor, MOSFET, current sensing and boost diode losses also influence the gain and compensation expressions. The OTA has an ESD protection structure (RESD ≈ 502 W, data not provided in the datasheet) located on the die between the OTA output and the IC package compensation pin (VC). The information from the OTA PWM feedback control signal (VCTRL) may differ from the IC−VC signal if R2 is of similar order of magnitude as RESD . The compensation and gain expressions which follow take influence from the OTA output impedance elements into account. Type−I compensation is not possible due to the presence of RESD . The Figure 13 compensation network corresponds to a Type−II network in series with RESD . The resulting control−output transfer function is an accurate mathematical model of the IC in a boost converter topology. The model 9. Select Diode The output diode rectifies the output current. The average current through diode will be equal to the output current: I D(avg) + I OUT(max) Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: V D(max) + V OUT(max) The maximum power dissipation in the diode can be calculated as follows: P D + V f (max) I OUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] The 4 amp, 40 V NRVB440MFS SO−8FL package Schottky diode is a recommended device. 10. Design Notes • VOUT serves a dual purpose (feedback and IC power). The VDRV circuit has a current pulse power draw resulting in current flow from the output sense location to the IC. Trace ESL will cause voltage ripple to www.onsemi.com 10 NCV8876 • The efficiency term h should be a reasonable operating does have limitations and a more accurate SPICE model should be considered for a more detailed analysis: • The attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor ESR is not considered in the equations. L rL VIN condition estimate. Vd VOUT rCf COUT GDRV R2 RGDRV RESD C2 C1 ROUT Rds(on) VC R1 VCTRL OTA R0 ISNS RLOW Ri VREF VOUT GND Figure 13. NCV8876 OTA and Compensation A worksheet as well as a SPICE model which may be used for selecting compensation components R2 , C1 , C2 is available at the onsemi web site (http://onsemi.com/PowerSolutions/product.do?id=NCV8 876). The following equations may be used to analyze the Figure 10 boost converter. Required input design parameters for analysis are: Vd = Boost diode Vf (V) VIN = Boost supply input voltage (V) Ri = Current sense resistor (W) RDS(on) = MOSFET RDS(on) (W) COUT = Bulk output capacitor value (F) Rsw_eq = RDS(on) + Ri, for the boost continuous conduction mode (CCM) expressions rCF = Bulk output capacitor ESR (W) ROUT = Equivalent resistance of output load (W) Pout = Output Power (W) L = Boost inductor value (H) rL = Boost inductor ESR (W) Ts = 1/fs, where fs = clock frequency (Hz) VOUT = Device specific output voltage (e.g. 6.8 V for NCV887601) (V) Vref = OTA internal voltage reference = 1.2 V R0 = OTA output resistance = 3 MW Sa = IC slope compensation (e.g. 53 mV/ms for NCV887601) gm = OTA transconductance = 1.2 mS D = Controller duty ratio D’ = 1 − D Necessary equations for describing the modulator gain (Vctrl−to−Vout gain) Hctrl_output(f) are described in Table 1. www.onsemi.com 11 NCV8876 Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS Duty ratio (D) ȡ ȧ ȧ ȧ Ȣ -V OUT ƪ ǒ V IN 2R OUTV dV IN* R sw_eq)R OUT *2 V OUT Ǹ ǒ R OUT V OUT 2 Ǔ ȣ ȧ ȧ ȧ Ȥ R OUTV IN 2)2R sw_eqV INV OUT*4V dR sw_eqV IN )R sw_eq 2V OUT 2 -4R sw_eqV OUT 2*4r LV dV IN*4r LV OUT 2 ǒ 2R OUT V OUT 2 ) V dV IN Vout/Vin DC Conversion Ratio (M) Ǔƫ Ǔ ȱ ȳ ȧ 1 ƪ1 * (1 *V D)V ƫȧȧ1 ) 1 1 ȧ 1*D ȧ ȧ r )DR (1*D) ǒ Ǔ R Ȳ ȴ d OUT sw_eq L 2 OUT P OUT Average Inductor Current (Ilave) V INh V IN * I Laveǒr L ) R sw_eqǓ Inductor On−slope (Sn) L Compensation Ramp (mc) 1) Sa Sn 1 r CFC OUT Cout ESR Zero (wz1) Right−half−plane Zero (wz2) (1 * D ) L 2 ǒ R OUT * 2 Low Frequency Modulator Pole (wp1) R OUT Ǔ r CFR OUT r CF ) R OUT ) Ts LM 3 * rL L mc C OUT p Ts Sampling Double Pole (wn) 1 Sampling Quality Coefficient (Qp) p(m c(1 * D) * 0.5) 1 Fm 2M ) R ǒ Ǔ T S OUT s 1 ) a 2 Sn LM 2 hR OUT Hd Control−output Transfer Function (Hctrl_output(f)) Ri Ri F mH d ǒ1 ) j z1Ǔ 2pf w ǒ1 * j z2Ǔ ǒ1 ) j Ǔ ǒ1 ) j 2pf w p1 2pf w 2pf w nQ p Ǔ ) ǒj 2pf wn Ǔ 2 Once the desired cross−over frequency (fc) gain adjustment and necessary phase boost are determined from the Hctrl_output(f) gain and phase plots, the Table 2 equations may be used. It should be noted that minor compensation component value adjustments may become necessary when R2 ≤ ~10 · Resd as a result of approximations for determining components R2, C1, C2. www.onsemi.com 12 NCV8876 Table 2. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES Desired OTA Gain at Cross−over Frequency fc (G) 10 ǒq Desired Phase Boost at Cross− over Frequency fc (boost) desired_G fc_gain_db 20 ǒHctrl_output(fc)Ǔ 180° * 90° Ǔ p margin * arg p 180° w p1e Select OTA Compensation Zero to Coincide with Modulator Pole at fp1 (fz) 2p Resulting OTA High Frequency Pole Placement (fp) f zf c ) f c 2 tan(boost) f c * f z tan(boost) Ǹ Compensation Resistor (R2) 1) V OUT f pG Ǹ f p * f z 1.2 g m 1) Compensation Capacitor (C1) 1 2pf zR 2 Compensation Capacitor (C2) 1.2 g m 1 2pf pG V OUT OTA DC Gain (G0_OTA) V ref V OUT Low Frequency Zero (wz1e) 1 2 High Frequency Zero (wz2e) ǒR 2 ) R esdǓȱ ȧ Ȳ ǒ Ǔȱ 1 R )R ȧ1 ) 2 R R C Ȳ ǒR ) R ) R Ǔȱ ȧ1 * R ǒR ) R ǓC Ȳ ǒR ) R ) R Ǔȱ ȧ1 ) R ǒR ) R ǓC Ȳ R 2R esdC 2 2 1* esd 2 esd 2 Low Frequency Pole (wp1e) 1 2 High Frequency Pole (wp2e) 1 2 0 2 2 0 0 2 esd esd 2 0 2 esd esd 2 OTA Transfer Function (GOTA(f)) Ǹ 1*4 Ǹ 1*4 Ǹ Ǹ 1*4 1*4 1 ) jw 1) fc 2 fp ǒǓ fz fp g mR 0 2pf −G 0_OTA ǒǓ z1e j w2pf p1e R 2R esdC 2 ǒR 2 ) R esdǓ 2 C1 R 2R esdC 2 ǒR 2 ) R esdǓ 2 C1 ȳ ȧ ȴ ȳ ȧ ȴ R 2ǒR 0 ) R esdǓC 2 ǒR 0 ) R 2 ) R esdǓ 2 C1 R 2ǒR 0 ) R esdǓC 2 ǒR 0 ) R 2 ) R esdǓ 2 C1 ȳ ȧ ȴ ȳ ȧ ȴ 2pf 1 ) jw 1) z2e j w2pf p2e The open−loop−response in closed−loop form to verify the gain/phase margins may be obtained from the following expressions. T(f) + G OTA(f)H ctrl_output(f) www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative