NDD01N60, NDT01N60
N-Channel Power MOSFET
600 V, 8.5 W
Features
• 100% Avalanche Tested
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
http://onsemi.com
Compliant
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Drain−to−Source Voltage
NDD
VDSS
NDT
600
ID
1.5
0.4
A
Continuous Drain Current RqJC
Steady State, TC = 100°C (Note 1)
ID
1.0
0.25
A
Pulsed Drain Current, tp = 10 ms
IDM
6.0
1.5
A
Power Dissipation – RqJC
Steady State, TC = 25°C
PD
46
2.5
W
Gate−to−Source Voltage
VGS
±30
V
Single Pulse Drain−to−Source
Avalanche Energy (IPK = 1.0 A)
EAS
13
mJ
Peak Diode Recovery (Note 2)
dv/dt
4.5
IS
Lead Temperature for Soldering
Leads
TL
260
°C
Operating Junction and Storage
Temperature
TJ, TSTG
−55 to +150
°C
0.4
THERMAL RESISTANCE
Junction−to−Ambient
D (2)
G (1)
S (3)
MARKING
DIAGRAMS
4
Drain
4
A
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Limited by maximum junction temperature
2. IS = 1.5 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS
Symbol
Value
Unit
NDD01N60
RqJC
2.7
°C/W
(Note 4) NDD01N60
(Note 3) NDD01N60−1
(Note 4) NDT01N60
(Note 5) NDT01N60
RqJA
38
96
58
141
°C/W
Junction−to−Case (Drain)
N−Channel MOSFET
V/ns
Source Current (Body Diode)
Parameter
8.5 W @ 10 V
V
Continuous Drain Current RqJC
Steady State, TC = 25°C (Note 1)
1.5
600 V
Unit
1 2
3
2
1 Drain 3
Gate Source
4
IPAK
CASE 369D
STYLE 2
1
2
12
4
Drain
3
Y
WW
G
= Year
= Work Week
= Pb−Free Package
4
3. Insertion mounted.
4. Surface−mounted on FR4 board using 1” sq. pad size
(Cu area = 1.127” sq. [2 oz] including traces).
5. Surface−mounted on FR4 board using minimum recommended pad size
(Cu area = 0.026” sq. [2 oz]).
DPAK
CASE 369C
STYLE 2
YWW
01
N60G
Symbol
RDS(ON) MAX
YWW
01
N60G
Parameter
V(BR)DSS
3
SOT−223
CASE 318E
STYLE 3
1 2 3
Gate Drain Source
Drain
4
AYW
01N60G
G
1
2
3
Gate Drain Source
A
= Assembly Location
Y
= Year
W
= Work Week
01N60 = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 2
1
Publication Order Number:
NDD01N60/D
NDD01N60, NDT01N60
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Conditions
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 1 mA
600
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Reference to 25°C, ID = 1 mA
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Leakage Current
Gate−to−Source Leakage Current
IDSS
VDS = 600 V, VGS = 0 V
V
660
mV/°C
TJ = 25°C
1
TJ = 125°C
50
IGSS
VGS = ±20 V
VGS(TH)
VDS = VGS, ID = 50 mA
±100
mA
nA
ON CHARACTERISTICS (Note 6)
Gate Threshold Voltage
2.2
3.3
3.7
VGS(TH)/TJ
Static Drain-to-Source On Resistance
RDS(on)
VGS = 10 V, ID = 0.2 A
8.0
gFS
VDS = 15 V, ID = 0.2 A
0.9
S
160
pF
Forward Transconductance
7.0
V
Negative Threshold Temperature Coefficient
mV/°C
8.5
W
CHARGES, CAPACITANCES & GATE RESISTANCES
Input Capacitance (Note 7)
Ciss
Output Capacitance (Note 7)
Coss
Reverse Transfer Capacitance (Note 7)
Crss
4.0
Total Gate Charge (Note 7)
Qg
7.2
Gate-to-Source Charge (Note 7)
Qgs
1.2
Gate-to-Drain Charge (Note 7)
Qgd
Plateau Voltage
VGP
4.5
V
Gate Resistance
Rg
6.7
W
td(on)
8.0
ns
VDS = 25 V, VGS = 0 V, f = 1 MHz
VDS = 300 V, ID = 0.4 A, VGS = 10 V
22
nC
3.1
SWITCHING CHARACTERISTICS (Note 8)
Turn-on Delay Time
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
VDD = 300 V, ID = 0.4 A,
VGS = 10 V, RG = 0 W
tf
5.1
16.5
21.3
DRAIN−SOURCE DIODE CHARACTERISTICS
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
Qrr
IS = 0.4 A, VGS = 0 V
TJ = 25°C
0.78
TJ = 125°C
0.63
1.6
179
VGS = 0 V, VDD = 30 V
IS = 1.0 A, di/dt = 100 A/ms
V
ns
37
141
288
nC
6. Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
7. Guaranteed by design.
8. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping†
NDD01N60−1G
IPAK
(Pb-Free, Halogen-Free)
75 Units / Rail
NDD01N60T4G
DPAK
(Pb-Free, Halogen-Free)
2500 / Tape & Reel
NDT01N60T1G
SOT−223
(Pb-Free, Halogen-Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
NDD01N60, NDT01N60
TYPICAL CHARACTERISTICS
2.0
5.5 V
VGS = 10 V
VDS ≥ 25 V
4.8 V
0.8
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
1.0
TJ = 25°C
4.6 V
0.6
0.4
4.4 V
0.2
4.2 V
1.6
1.2
TJ = 25°C
0.8
TJ = −55°C
TJ = 125°C
0.4
4.0 V
0
5
10
15
20
0
25
9.0
8.5
8.0
7.5
7.0
6
7
8
9
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
16
VGS = 10 V
TJ = 25°C
14
12
10
8
6
0
0.5
1.0
1.5
2.0
2.5
3.0
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
2.4
ID = 200 mA
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
5
Figure 2. Transfer Characteristics
ID = 200 mA
TJ = 25°C
2.0
4
Figure 1. On−Region Characteristics
9.5
4
3
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
6.5
2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
1.6
1.2
VGS = 0 V
1000
TJ = 150°C
TJ = 125°C
100
0.8
0.4
−50
−25
0
25
50
75
100
125
150
10
0
100
200
300
400
500
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
600
NDD01N60, NDT01N60
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
Ciss
10
Coss
Crss
VGS = 0 V
TJ = 25°C
f = 1 MHz
1
1
10
VDS
6
Qgs
150
0
0
1
2
3
4
5
6
7
50
8
0
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
3.5
tf
td(off)
td(on)
0.1
1
10
VGS = 0 V
TJ = 25°C
3.0
IS, SOURCE CURRENT (A)
2.5
2.0
1.5
1.0
0.5
0
100
0
0.2
0.4
0.6
0.8
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
10
10
VGS = 10 V
Single Pulse
TC = 25°C
TJ = 150°C
1
10 ms
100 ms
1 ms
10 ms
0.1
dc
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
100
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
100
VDS = 300 V
TJ = 25°C
ID = 400 mA
2
QG, TOTAL GATE CHARGE (nC)
tr
ID, DRAIN CURRENT (A)
200
Qgd
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
0.01
250
4
100
VDS = 300 V
ID = 400 mA
VGS = 10 V
1
300
8
1000
10
350
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
RDS(on) Limit
Thermal Limit
Package Limit
1 ms
100 ms
1
10 ms
0.1
0.01
VGS = 10 V
Single Pulse
TC = 25°C
TJ = 150°C
0.1
1
10
dc
100
1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area NDD01N60
Figure 12. Maximum Rated Forward Biased
Safe Operating Area NDT01N60
http://onsemi.com
4
NDD01N60, NDT01N60
TYPICAL CHARACTERISTICS
10
R(t) (°C/W)
50% Duty Cycle
1 20%
0.1
10%
5%
2%
1%
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
1
10
100
1000
100
1000
PULSE TIME (sec)
Figure 13. Thermal Impedance (Junction−to−Case) for NDD01N60
100
R(t) (°C/W)
50% Duty Cycle
20%
10 10%
5%
2%
1 1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
PULSE TIME (sec)
Figure 14. Thermal Impedance (Junction−to−Ambient) for NDT01N60
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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