NDD02N40T4G

NDD02N40, NDT02N40 N-Channel Power MOSFET 400 V, 5.5 W Features • 100% Avalanche Tested • These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS http://onsemi.com Compliant V(BR)DSS RDS(ON) MAX 400 V 5.5 W @ 10 V ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) NDD NDT Unit Drain−to−Source Voltage VDSS 400 V Gate−to−Source Voltage VGS ±20 V Continuous Drain Current RqJC Steady State, TC = 25°C (Note 1) ID 1.7 0.4 A Continuous Drain Current RqJC Steady State, TC = 100°C (Note 1) ID 1.1 0.25 A Power Dissipation – RqJC Steady State, TC = 25°C PD 39 2.0 W Pulsed Drain Current IDM 6.9 1.6 A IS 1.7 0.4 A Continuous Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy, ID = 1 A Maximum Temperature for Soldering Leads Operating Junction and Storage Temperature EAS 120 mJ TL 260 °C TJ, TSTG −55 to +150 °C N−Channel MOSFET D (2) G (1) S (3) MARKING DIAGRAMS 4 Drain 4 1 2 3 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. IS = 1.7 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C THERMAL RESISTANCE 1 Parameter Junction−to−Case (Drain) 4 Symbol NDD02N40 RqJC Junction−to−Ambient Steady State NDD02N40 (Note 4) NDD02N40−1 (Note 3) NDT02N40 (Note 4) NDT02N40 (Note 5) RqJA Value 3.2 2 °C/W Y WW 2N40 G °C/W 3. Insertion mounted 4. Surface mounted on FR4 board using 1″ sq. pad size (Cu area = 1.127″ sq. [2 oz] including traces) 5. Surface−mounted on FR4 board using minimum recommended pad size (Cu area = 0.026” sq. [2 oz]). 2 1 3 Drain Gate Source 4 Drain IPAK CASE 369D (Straight Lead) STYLE 2 Unit 39 96 62 151 DPAK CASE 369C (Surface Mount) STYLE 2 YWW 2N 40G Symbol YWW 2N 40G Parameter 3 = Year 1 2 3 = Work Week Gate Drain Source = Device Code = Pb−Free Package Drain 4 SOT−223 4 CASE 318E AYW 12 STYLE 3 3 2N40G A = Assembly Location G Y = Year 1 2 3 W = Work Week Gate Drain Source 2N40 = Specific Device Code G = Pb−Free Package (*Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 4 1 Publication Order Number: NDD02N40/D NDD02N40, NDT02N40 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 1 mA 400 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Reference to 25°C, ID = 1 mA Characteristic Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current Gate−to−Source Leakage Current IDSS VDS = 400 V, VGS = 0 V V 460 TJ = 25°C 1 TJ = 125°C 50 VGS = ±20 V IGSS mV/°C ±10 mA mA ON CHARACTERISTICS (Note 6) VGS(TH) VDS = VGS, ID = 250 mA Negative Threshold Temperature Coefficient VGS(TH)/TJ Reference to 25°C, ID = 50 mA 4.6 Static Drain-to-Source On Resistance RDS(on) VGS = 10 V, ID = 0.22 A 4.5 gFS VDS = 15 V, ID = 0.22 A 1.1 S 121 pF Gate Threshold Voltage Forward Transconductance 0.8 1.6 2 V mV/°C 5.5 W DYNAMIC CHARACTERISTICS Input Capacitance (Note 7) Ciss Output Capacitance (Note 7) Coss Reverse Transfer Capacitance (Note 7) Crss Total Gate Charge (Note 7) Qg VDS = 25 V, VGS = 0 V, f = 1 MHz 16 3 nC 5.5 Gate-to-Source Charge (Note 7) Qgs Gate-to-Drain (“Miller”) Charge (Note 7) Qgd 0.8 Plateau Voltage VGP 3.1 V Gate Resistance Rg 8.7 W 5 ns VDS = 200 V, ID = 1.7 A, VGS = 10 V 1.0 RESISTIVE SWITCHING CHARACTERISTICS (Note 8) Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time td(on) tr td(off) VDD = 200 V, ID = 1.7 A, VGS = 10 V, RG = 0 W tf 7 14 4 SOURCE−DRAIN DIODE CHARACTERISTICS Diode Forward Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time tb Reverse Recovery Charge Qrr IS = 1.7 A, VGS = 0 V TJ = 25°C TJ = 100°C 0.9 V 0.8 146 VGS = 0 V, VDD = 30 V, IS = 1.7 A, di/dt = 100 A/ms 1.6 ns 37 109 260 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 7. Guaranteed by design. 8. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NDD02N40, NDT02N40 ORDERING INFORMATION Package Shipping† NDD02N40−1G IPAK (Pb−Free, Halogen Free) 75 Units / Rail NDD02N40T4G DPAK (Pb−Free, Halogen Free) 2500 / Tape & Reel NDT02N40T1G SOT−223 (Pb−Free, Halogen Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NDD02N40, NDT02N40 TYPICAL CHARACTERISTICS 2.5 VGS = 7 V to 10 V 3.2 V 3.4 V to 3.5 V 3.0 V 1.5 2.8 V 1.0 2.6 V 0.5 2.0 V TJ = −55°C VDS = 25 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 2.0 2.4 V 2.0 TJ = 25°C 1.5 TJ = 150°C 1.0 0.5 2.2 V 0 0 0 5 10 15 20 25 1.0 2.5 3.0 3.5 4.0 4.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 5.0 12 ID = 0.22 A TJ = 25°C 11 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 2.0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 12 10 9 8 7 6 5 VGS = 10 V TJ = 25°C 11 10 9 8 7 6 5 4 4 2 3 4 5 6 7 8 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 10 9 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.25 VGS = 10 V ID = 0.22 A 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 125 150 NORMALIZED BREAKDOWN VOLTAGE (V) VGS, GATE−TO−SOURCE (V) 2.50 RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) 1.5 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. Normalized BVDSS with Temperature http://onsemi.com 4 NDD02N40, NDT02N40 TYPICAL CHARACTERISTICS 1000 1 C, CAPACITANCE (pF) IDSS, LEAKAGE (mA) TJ = 150°C 0.1 TJ = 125°C CISS 100 COSS 10 CRSS 1 0.01 0 50 100 200 250 300 100 Figure 7. Drain−to−Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 400 350 VGS 8 300 7 6 250 200 QGS VDS = 200 V TJ = 25°C ID = 1.7 A QGD 3 2 1 0 150 100 VDS 50 0 1 2 3 4 5 100 VGS = 10 V VDD = 200 V ID = 1.7 A t, TIME (ns) 450 10 9 td(off) 10 tr td(on) tf 1 1 6 10 100 QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (W) Figure 9. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 10 ID, DRAIN CURRENT (A) 100 IS, SOURCE CURRENT (A) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QT 0 1 400 350 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) 150 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 12 11 5 4 VGS = 0 V TJ = 25°C f = 1 MHz 10 TJ = 150°C TJ = −55°C 1 TJ = 25°C TJ = 125°C 0.1 0.5 0.6 0.7 VGS ≤ 30 V Single Pulse TC = 25°C 10 ms 100 ms 1 ms 1 10 ms dc 0.1 RDS(on) Limit Thermal Limit Package Limit 0.01 0.1 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1 10 100 1000 VSD, SOURCE−TO−DRAIN VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Diode Forward Voltage vs. Current Figure 12. Maximum Rated Forward Biased Safe Operating Area for NDD02N40 http://onsemi.com 5 NDD02N40, NDT02N40 TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 10 RDS(on) Limit Thermal Limit Package Limit 10 ms 1 1 ms 100 ms 0.1 0.01 0.1 10 ms VGS ≤ 30 V Single Pulse TC = 25°C 1 dc 10 100 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area for NDT02N40 10 R(t) (°C/W) Duty Cycle = 0.5 1 0.2 0.1 0.05 0.02 RqJC = 3.2°C/W Steady State 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 14. Thermal Impedance (Junction−to−Case) for NDD02N40 100 Duty Cycle = 0.5 R(t) (°C/W) 10 1 0.2 0.1 0.05 0.02 0.01 0.1 Single Pulse RqJA = 62°C/W Steady State 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 PULSE TIME (sec) Figure 15. Thermal Impedance (Junction−to−Ambient) for NDT02N40 http://onsemi.com 6 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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