NDDL01N60ZT4G

NDDL01N60Z, NDTL01N60Z N-Channel Power MOSFET 600 V, 15 W Features • • • • 100% Avalanche Tested Gate Charge Minimized Zener−protected These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com V(BR)DSS RDS(ON) MAX 600 V 15 W @ 10 V ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol NDD NDT Unit Drain−to−Source Voltage VDSS 600 V Gate−to−Source Voltage VGS ±30 V Continuous Drain Current Steady State, TC = 25°C (Note 1) ID 0.8 0.25 A Continuous Drain Current Steady State, TC = 100°C (Note 1) ID 0.5 0.15 A Power Dissipation Steady State, TC = 25°C PD 26 2 W Pulsed Drain Current, tp = 10 ms IDM G (1) 2.5 A IS Single Pulse Drain−to−Source Avalanche Energy (ID = 0.8 A) EAS Peak Diode Recovery (Note 2) dv/dt 4.5 V/ns Lead Temperature for Soldering Leads TL 260 °C Operating Junction and Storage Temperature TJ, TSTG −55 to +150 °C 1.7 A 12 4 mJ 12 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. IS = 1.5 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS THERMAL RESISTANCE Parameter Junction−to−Ambient D (2, 4) S (3) 3.4 Source Current (Body Diode) Symbol Value Unit NDDL1N60Z RqJC 4.8 °C/W (Note 4) NDDL1N60Z (Note 3) NDDL1N60Z−1 (Note 4) NDTL1N60Z (Note 5) NDTL1N60Z RqJA 42 96 62 151 °C/W Junction−to−Case (Drain) N−Channel MOSFET 3 SOT−223 CASE 318E STYLE 3 4 4 1 2 1 3 DPAK CASE 369C STYLE 2 2 3 IPAK CASE 369D STYLE 2 MARKING & ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 3 of this data sheet. 3. Insertion mounted. 4. Surface−mounted on FR4 board using 1” sq. pad size (Cu area = 1.127” sq. [2 oz] including traces). 5. Surface−mounted on FR4 board using minimum recommended pad size (Cu area = 0.026” sq. [2 oz]). © Semiconductor Components Industries, LLC, 2014 May, 2014 − Rev. 0 1 Publication Order Number: NDDL01N60Z/D NDDL01N60Z, NDTL01N60Z ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 1 mA 600 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Reference to 25°C, ID = 1 mA Characteristic Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current Gate−to−Source Leakage Current IDSS VDS = 600 V, VGS = 0 V V 610 mV/°C TJ = 25°C 1 TJ = 125°C 50 IGSS VGS = ±20 V ±100 VGS(TH) VDS = VGS, ID = 50 mA mA nA ON CHARACTERISTICS (Note 6) Gate Threshold Voltage 3 4.0 4.5 VGS(TH)/TJ Static Drain-to-Source On Resistance RDS(on) VGS = 10 V, ID = 0.4 A 12.2 gFS VDS = 15 V, ID = 0.4 A 0.7 S 92 pF Forward Transconductance 9.6 V Negative Threshold Temperature Coefficient mV/°C 15 W CHARGES, CAPACITANCES & GATE RESISTANCES Input Capacitance (Note 7) Ciss Output Capacitance (Note 7) Coss Reverse Transfer Capacitance (Note 7) Crss Effective output capacitance, energy related (Note 9) Co(er) Effective output capacitance, time related (Note 10) Co(tr) VDS = 25 V, VGS = 0 V, f = 1 MHz 13 3 VGS = 0 V, VDS = 0 to 480 V ID = constant, VGS = 0 V, VDS = 0 to 480 V pF 5.5 8.1 nC Total Gate Charge (Note 7) Qg 4.9 Gate-to-Source Charge (Note 7) Qgs 1.2 Gate-to-Drain Charge (Note 7) Qgd Plateau Voltage VGP 5.8 V Gate Resistance Rg 6.6 W td(on) 10 ns VDS = 300 V, ID = 0.4 A, VGS = 10 V 2.4 SWITCHING CHARACTERISTICS (Note 8) Turn-on Delay Time Rise Time Turn-off Delay Time tr td(off) Fall Time VDD = 300 V, ID = 0.4 A, VGS = 10 V, RG = 0 W tf 5 13 18 DRAIN−SOURCE DIODE CHARACTERISTICS Diode Forward Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time tb Reverse Recovery Charge Qrr IS = 0.4 A, VGS = 0 V TJ = 25°C TJ = 100°C 0.8 V 0.7 183 VGS = 0 V, VDD = 30 V IS = 1 A, di/dt = 100 A/ms 1.2 ns 33 150 255 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 7. Guaranteed by design. 8. Switching characteristics are independent of operating junction temperatures. 9. Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% V(BR)DSS 10. Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% V(BR)DSS http://onsemi.com 2 NDDL01N60Z, NDTL01N60Z MARKING DIAGRAMS 4 Drain YWW L1N 60ZG YWW L1N 60ZG 4 Drain Drain 4 1 2 3 Gate Drain Source 2 1 Drain 3 Gate Source AYW 1N60ZG G 1 2 3 Gate Drain Source IPAK DPAK SOT−223 A = Assembly Location Y = Year W, WW = Work Week L1N60Z, 1N60Z = Specific Device Codes G or G = Pb−Free Package (*Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NDDL01N60Z−1G IPAK (Pb-Free, Halogen-Free) 75 Units / Rail NDDL01N60ZT4G DPAK (Pb-Free, Halogen-Free) 2500 / Tape & Reel NDTL01N60ZT1G SOT−223 (Pb-Free, Halogen-Free) 1000 / Tape & Reel NDTL01N60ZT3G SOT−223 (Pb-Free, Halogen-Free) 4000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NDDL01N60Z, NDTL01N60Z TYPICAL CHARACTERISTICS 1.4 1.4 VGS = 10 V to 7.0 V 1.0 VGS = 6.5 V 0.8 VGS = 6.0 V 0.6 0.4 VGS = 5.5 V VGS = 5.0 V 0 TJ = 25°C 0.8 0.6 TJ = 150°C 0.4 5 10 15 20 25 2 30 6 5 8 7 9 10 1.2 1.4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 0.4 A 21 19 17 15 13 11 5 6 7 8 9 10 Figure 3. On−Resistance vs. Gate−to−Source Voltage 2.6 ID = 0.4 A VGS = 10 V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 −25 0 25 50 75 100 125 150 BVDSS, NORMALIZED BREAKDOWN VOLTAGE VGS, GATE VOLTAGE (V) 0.6 0.4 −50 4 VGS, GATE−TO−SOURCE VOLTAGE (V) 23 2.2 3 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 25 2.4 TJ = −55°C 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 1.0 0.2 0.2 RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE VDS = 15 V 1.2 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 1.2 25 23 TJ = 25°C VGS = 10 V 21 19 17 15 13 11 0 0.2 0.4 1.0 0.8 0.6 ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.125 1.100 ID = 1 mA 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. Breakdown Voltage Variation with Temperature http://onsemi.com 4 150 NDDL01N60Z, NDTL01N60Z 10,000 1.15 ID = 50 mA 1.10 1.05 IDSS, LEAKAGE (nA) 1.00 0.95 0.90 0.85 0.80 0.70 0.65 −50 100 TJ = 125°C TJ = 100°C 10 1 −25 0 25 50 75 100 0 150 125 100 200 300 400 500 600 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Threshold Voltage Variation with Temperature Figure 8. Drain−to−Source Leakage Current vs. Voltage 12 VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) TJ = 150°C 0.75 1000 VGS = 0 V TJ = 25°C f = 1 MHz CISS 100 COSS 10 CRSS 0.1 1 10 100 11 300 250 VGS 200 QGD QGS 6 5 150 4 3 VDS = 300 V TJ = 25°C ID = 0.4 A 2 1 0 100 50 0 0 1000 350 QT VDS 10 9 8 7 1 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 9. Capacitance Variation Figure 10. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 10 100 TJ = 100°C IS, SOURCE CURRENT (A) VGS = 10 V VDD = 300 V ID = 0.8 A td(off) t, TIME (ns) 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS(th), NORMALIZED THRESHOLD VOLTAGE TYPICAL CHARACTERISTICS tf td(on) 10 tr TJ = 125°C 1 0.1 TJ = 150°C TJ = 25°C 0.01 TJ = −55°C 0.001 1 0.1 1 10 0.2 0.3 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 5 NDDL01N60Z, NDTL01N60Z TYPICAL CHARACTERISTICS 10 VGS ≤ 30 V Single Pulse TC = 25°C 1 10 ms 100 ms 1 ms 10 ms dc 0.1 0.01 RDS(on) Limit Thermal Limit Package Limit 0.001 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 VGS ≤ 30 V Single Pulse TC = 25°C 1 10 ms 100 ms 1 ms 10 ms 0.1 dc 0.01 RDS(on) Limit Thermal Limit Package Limit 0.001 0.1 1 10 100 1000 0.1 1 10 100 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area for NDDL01N60Z Figure 14. Maximum Rated Forward Biased Safe Operating Area for NDTL01N60Z R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) 10 Duty Cycle = 0.5 RqJC steady state = 4.8°C/W 0.20 1 0.10 0.05 0.02 0.01 0.1 Single Pulse 0.01 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 t, TIME (s) Figure 15. Thermal Impedance (Junction−to−Case) for NDDL01N60Z 100 R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) Duty Cycle = 0.5 0.20 10 0.10 0.05 RqJA steady state = 62°C/W 0.02 1 0.01 0.1 Single Pulse 0.01 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 t, TIME (s) Figure 16. Thermal Impedance (Junction−to−Ambient) for NDTL01N60Z http://onsemi.com 6 1E+02 1E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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