NDF02N60Z, NDD02N60Z
N-Channel Power MOSFET
600 V, 4.8 W
Features
•
•
•
•
•
Low ON Resistance
Low Gate Charge
ESD Diode−Protected Gate
100% Avalanche Tested
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
VDSS
RDS(on) (MAX) @ 1 A
600 V
4.8 W
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain−to−Source Voltage
NDF
VDSS
NDD
600
D (2)
V
Continuous Drain Current RqJC
(Note 1)
ID
2.4
2.2
A
Continuous Drain Current RqJC
TA = 100°C (Note 1)
ID
1.6
1.4
A
Pulsed Drain Current, VGS @ 10 V
IDM
10
9
A
Power Dissipation RqJC
PD
24
57
W
Gate−to−Source Voltage
VGS
±30
V
Single Pulse Avalanche Energy,
ID = 2.4 A
EAS
120
mJ
ESD (HBM)
(JESD 22−A114)
Vesd
2500
V
RMS Isolation Voltage
(t = 0.3 sec., R.H. ≤ 30%,
TA = 25°C) (Figure 17)
VISO
Peak Diode Recovery (Note 2)
dv/dt
4.5
V/ns
Continuous Source Current (Body
Diode)
IS
2.4
A
Maximum Temperature for Soldering
Leads
TL
260
°C
TJ, Tstg
−55 to 150
°C
Operating Junction and
Storage Temperature Range
N−Channel
Unit
4500
G (1)
S (3)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Limited by maximum junction temperature
2. ISD = 2.4 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C
1
2
3
NDF02N60ZG,
NDF02N60ZH
TO−220FP
CASE 221AH
4
4
1
2
3
NDD02N60Z−1G
IPAK
CASE 369D
1 2
3
NDD02N60ZT4G
DPAK
CASE 369AA
ORDERING AND MARKING INFORMATION
See detailed ordering, marking and shipping information on
page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2014 − Rev. 8
1
Publication Order Number:
NDF02N60Z/D
NDF02N60Z, NDD02N60Z
THERMAL RESISTANCE
Parameter
Junction−to−Case (Drain)
Junction−to−Ambient Steady State
Symbol
Value
Unit
NDF02N60Z
NDD02N60Z
RqJC
4.9
2.2
°C/W
(Note 3) NDF02N60Z
(Note 4) NDD02N60Z
(Note 3) NDD02N60Z−1
RqJA
51
41
80
3. Insertion mounted
4. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Test Conditions
Symbol
Min
VGS = 0 V, ID = 1 mA
BVDSS
600
Reference to 25°C,
ID = 1 mA
DBVDSS/
DTJ
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Drain−to−Source Leakage Current
VDS = 600 V, VGS = 0 V
Gate−to−Source Forward Leakage
25°C
V
0.6
IDSS
V/°C
1
150°C
mA
50
VGS = ±20 V
IGSS
Static Drain−to−Source On−Resistance
VGS = 10 V, ID = 1.0 A
RDS(on)
Gate Threshold Voltage
VDS = VGS, ID = 50 mA
VGS(th)
Forward Transconductance
VDS = 15 V, ID = 1.2 A
gFS
±10
mA
4.0
4.8
W
4.0
4.5
V
ON CHARACTERISTICS (Note 5)
3.0
1.7
S
DYNAMIC CHARACTERISTICS
Input Capacitance (Note 6)
Output Capacitance (Note 6)
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Ciss
215
274
325
Coss
25
34
45
Reverse Transfer Capacitance (Note 6)
Crss
4.0
7.0
10
Total Gate Charge (Note 6)
Qg
5.0
10
16
Qgs
1.5
2.4
4.0
Qgd
3.5
5.3
8.0
Gate−to−Source Charge (Note 6)
Gate−to−Drain (“Miller”) Charge (Note 6)
VDD = 300 V, ID = 2.4 A,
VGS = 10 V
pF
nC
Plateau Voltage
VGP
6.4
V
Gate Resistance
Rg
4.9
W
td(on)
9.0
ns
tr
7.0
RESISTIVE SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
VDD = 300 V, ID = 2.4 A,
VGS = 10 V, RG = 5 W
Fall Time
td(off)
15
tf
7.0
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted)
Diode Forward Voltage
IS = 2.4 A, VGS = 0 V
VSD
Reverse Recovery Time
VGS = 0 V, VDD = 30 V
IS = 2.4 A, di/dt = 100 A/ms
trr
240
ns
Qrr
0.7
mC
Reverse Recovery Charge
1.6
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%.
6. Guaranteed by design.
www.onsemi.com
2
NDF02N60Z, NDD02N60Z
TYPICAL CHARACTERISTICS
4.0
4.0
3.5
7.0 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
3.5
3.0
VGS = 10 V
2.5
6.5 V
2.0
6.0 V
1.5
1.0
5.5 V
0.5
0.0
0.0
VDS = 25 V
3.0
2.5
2.0
1.5
TJ = 25°C
1.0
TJ = 150°C
0.5
5.0 V
5.0
10.0
15.0
20.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
25.0
0.0
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
6.00
ID = 1 A
TJ = 25°C
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
Figure 3. On−Region versus Gate−to−Source
Voltage
2.50
2.25
2.00
ID = 1 A
VGS = 10 V
1.75
1.50
1.25
1.00
0.75
0.50
0.25
−50
−25
0
25
50
75
100
125
10
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
5.75
TJ = −55°C
150
TJ, JUNCTION TEMPERATURE (°C)
5.25
5.00
VGS = 10 V
TJ = 25°C
4.75
4.50
4.25
4.00
3.75
0.0
0.3
0.5
0.8
1.0
1.3
1.5
1.8
2.0
2.3
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance versus Drain
Current and Gate Voltage
1.15
ID = 1 mA
1.10
1.05
1.00
0.95
0.90
−50
Figure 5. On−Resistance Variation with
Temperature
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. BVDSS Variation with Temperature
www.onsemi.com
3
2.5
150
NDF02N60Z, NDD02N60Z
TYPICAL CHARACTERISTICS
600
10
550
TJ = 25°C
VGS = 0 V
f = 1 MHz
C, CAPACITANCE (pF)
TJ = 150°C
1.0
TJ = 125°C
450
400
350
300
Ciss
250
200
150
100
50
0
0
50 100 150 200 250 300 350 400 450 500 550 600
0
5
10
15
20
25
30
35
40
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Drain−to−Source Leakage Current
versus Voltage
Figure 8. Capacitance Variation
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.10
Coss
Crss
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
350
QT
300
VDS
250
VGS
QGS
200
QGD
150
VDS = 300 V
ID = 2.4 A
TJ = 25°C
0
1
2
3
4
5
6
7
8
9
10
100
50
0
11
45
50
1.1
1.2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IDSS, LEAKAGE (mA)
500
Qg, TOTAL GATE CHARGE (nC)
Figure 9. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
10.0
1000
IS, SOURCE CURRENT (A)
t, TIME (ns)
VDD = 300 V
ID = 2.4 A
VGS = 10 V
100
td(off)
tr
tf
td(on)
10
TJ = 150°C
1.0
125°C
25°C
−55°C
1.0
1
10
0.1
0.3
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
Figure 11. Diode Forward Voltage versus
Current
www.onsemi.com
4
NDF02N60Z, NDD02N60Z
TYPICAL CHARACTERISTICS
100
VGS v 30 V
SINGLE PULSE
TC = 25°C
10
100 ms
1 ms
10 ms
1
dc
0.1
0.01
10 ms
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
10
100
1000
10
VGS v 30 V
SINGLE PULSE
TC = 25°C
1
100 ms
1 ms
10 ms
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10 ms
1
10
100
1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area NDD02N60Z
Figure 13. Maximum Rated Forward Biased
Safe Operating Area NDF02N60Z
10
R(t) (C/W)
1
50% (DUTY CYCLE)
20%
10%
0.1
5%
2%
1%
RqJC = 2.2°C/W
Steady State
SINGLE PULSE
0.01
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
PULSE TIME (s)
Figure 14. Thermal Impedance (Junction−to−Case) for NDD02N60Z
R(t) (C/W)
100
10 50% (DUTY CYCLE)
20%
10%
5.0%
1
2.0%
1.0%
0.1
0.01
1E−06
RqJA = 41°C/W
Steady State
SINGLE PULSE
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
PULSE TIME (s)
Figure 15. Thermal Impedance (Junction−to−Ambient) for NDD02N60Z
www.onsemi.com
5
1E+02
1E+03
NDF02N60Z, NDD02N60Z
10
50% (DUTY CYCLE)
R(t) (C/W)
1
20%
10%
5%
2%
0.1
1%
RqJC = 4.9°C/W
Steady State
SINGLE PULSE
0.01
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
PULSE TIME (s)
Figure 16. Thermal Impedance (Junction−to−Case) for NDF02N60Z
LEADS
HEATSINK
0.110″ MIN
Figure 17. Isolation Test Diagram
Measurement made between leads and heatsink with all leads shorted together.
*For additional mounting information, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
6
1E+02
1E+03
NDF02N60Z, NDD02N60Z
ORDERING INFORMATION
Package
Shipping†
NDF02N60ZG
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
NDF02N60ZH
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
NDD02N60Z−1G
IPAK
(Pb−Free, Halogen−Free)
75 Units / Rail
NDD02N60ZT4G
DPAK
(Pb−Free, Halogen−Free)
2500 / Tape and Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
4
Drain
4
Drain
YWW
2N
60ZG
Gate
YWW
2N
60ZG
NDF02N60ZG
or
NDF02N60ZH
AYWW
Source
1 2 3
Gate Drain Source
Drain
TO−220FP
IPAK
A
Y
WW
G, H
= Location Code
= Year
= Work Week
= Pb−Free, Halogen−Free Package
www.onsemi.com
7
2
1 Drain 3
Gate Source
DPAK
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220 FULLPACK, 3−LEAD
CASE 221AH
ISSUE F
A
E
B
P
E/2
0.14
SCALE 1:1
Q
D
M
B A
A
H1
M
A1
C
NOTE 3
1 2 3
L
L1
3X
3X
SEATING
PLANE
b2
c
b
0.25
M
B A
M
C
A2
e
SIDE VIEW
FRONT VIEW
SECTION D−D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR UNCONTROLLED IN THIS AREA.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE
PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO
EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA
SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY.
5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION.
LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00.
6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY
MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1
AND H1 FOR MANUFACTURING PURPOSES.
MILLIMETERS
MIN
MAX
4.30
4.70
2.50
2.90
2.50
2.90
0.54
0.84
1.10
1.40
0.49
0.79
14.70
15.30
9.70
10.30
2.54 BSC
6.60
7.10
12.50
14.73
--2.80
3.00
3.40
2.80
3.20
DIM
A
A1
A2
b
b2
c
D
E
e
H1
L
L1
P
Q
GENERIC
MARKING DIAGRAM*
A
NOTE 6
DATE 30 SEP 2014
NOTE 6
H1
D
D
XX
XXXXXXXXX
AWLYWWG
A
SECTION A−A
ALTERNATE CONSTRUCTION
1
STYLE 1:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. GATE
DOCUMENT NUMBER:
98AON52577E
DESCRIPTION:
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
TO−220 FULLPACK, 3−LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
