NDF03N60ZH

NDF03N60Z, NDD03N60Z N-Channel Power MOSFET 600 V, 3.6 W Features • • • • • Low ON Resistance Low Gate Charge ESD Diode−Protected Gate 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com VDSS RDS(on) (MAX) @ 1.2 A 600 V 3.6 W ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Drain−to−Source Voltage NDF VDSS NDD 600 D (2) V Continuous Drain Current RqJC ID 3.1 (Note 1) 2.6 A Continuous Drain Current RqJC TA = 100°C ID 2.9 (Note 1) 1.65 A Pulsed Drain Current, VGS @ 10 V IDM 12 10 A Power Dissipation RqJC PD 27 61 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy, ID = 3.0 A EAS 100 mJ ESD (HBM) (JESD 22−A114) Vesd 3000 V RMS Isolation Voltage (t = 0.3 sec., R.H. ≤ 30%, TA = 25°C) (Figure 17) VISO Peak Diode Recovery (Note 2) dv/dt 4.5 V/ns Continuous Source Current (Body Diode) IS 3.0 A Maximum Temperature for Soldering Leads TL 260 °C TJ, Tstg −55 to 150 °C Operating Junction and Storage Temperature Range N−Channel Unit 4500 G (1) S (3) V 1 2 3 NDF03N60ZG, NDF03N60ZH TO−220FP CASE 221AH Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. ISD = 3.0 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C 4 4 1 1 2 2 3 3 NDD03N60Z−1G IPAK CASE 369D NDD03N60ZT4G DPAK CASE 369AA MARKING AND ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 8 1 Publication Order Number: NDF03N60Z/D NDF03N60Z, NDD03N60Z THERMAL RESISTANCE Parameter Symbol Value Unit NDF03N60Z NDD03N60Z RqJC 4.7 2.0 °C/W (Note 3) NDF03N60Z (Note 4) NDD03N60Z (Note 3) NDD03N60Z−1 RqJA 51 40 80 Junction−to−Case (Drain) Junction−to−Ambient Steady State 3. Insertion mounted 4. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Test Conditions Symbol Min Drain−to−Source Breakdown Voltage VGS = 0 V, ID = 1 mA BVDSS 600 Breakdown Voltage Temperature Coefficient Reference to 25°C, ID = 1 mA DBVDSS/ DTJ Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current 25°C VDS = 600 V, VGS = 0 V Gate−to−Source Forward Leakage V 0.6 IDSS V/°C 1 150°C mA 50 VGS = ±20 V IGSS Static Drain−to−Source On−Resistance VGS = 10 V, ID = 1.2 A RDS(on) Gate Threshold Voltage VDS = VGS, ID = 50 mA VGS(th) Forward Transconductance VDS = 15 V, ID = 1.5 A gFS ±10 mA 3.3 3.6 W 3.9 4.5 V ON CHARACTERISTICS (Note 5) 3.0 2.0 S DYNAMIC CHARACTERISTICS Input Capacitance (Note 6) Output Capacitance (Note 6) VDS = 25 V, VGS = 0 V, f = 1.0 MHz Reverse Transfer Capacitance (Note 6) Total Gate Charge (Note 6) Gate−to−Source Charge (Note 6) VDD = 300 V, ID = 3.0 A, VGS = 10 V Gate−to−Drain (“Miller”) Charge (Note 6) Ciss 248 312 372 Coss 30 39 50 Crss 4 8 12 Qg 6 12 18 Qgs 1.5 2.5 4 Qgd 3 6.1 9 pF nC Plateau Voltage VGP 6.4 V Gate Resistance Rg 6.0 W td(on) 9 ns tr 8 td(off) 16 tf 10 RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time VDD = 300 V, ID = 3.0 A, VGS = 10 V, RG = 5 W Fall Time SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage IS = 3.0 A, VGS = 0 V VSD Reverse Recovery Time VGS = 0 V, VDD = 30 V IS = 3.0 A, di/dt = 100 A/ms trr 265 ns Qrr 0.9 mC Reverse Recovery Charge 1.6 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 6. Guaranteed by design. www.onsemi.com 2 NDF03N60Z, NDD03N60Z TYPICAL CHARACTERISTICS 4.0 4.0 7.0 V 3.0 VDS = 25 V 3.5 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 3.5 6.5 V VGS = 10 V 2.5 6.0 V 2.0 1.5 1.0 5.5 V 3.0 2.5 2.0 1.5 TJ = 25°C TJ = 150°C 1.0 TJ = −55°C 0.5 0.5 5.0 V 0.0 0.0 5.0 10.0 15.0 20.0 25.0 0.0 3 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 4.50 4.25 4.00 3.75 3.50 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 7 8 9 5.00 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.50 2.25 2.00 ID = 1.2 A VGS = 10 V 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 125 10 VGS = 10 V TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (V) 150 BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = 1.2 A TJ = 25°C 6.0 6 Figure 2. Transfer Characteristics 5.00 3.25 5.5 5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics 4.75 4 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. BVDSS Variation with Temperature www.onsemi.com 3 3.5 150 NDF03N60Z, NDD03N60Z TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) IDSS, LEAKAGE (mA) 10 TJ = 150°C 1.0 TJ = 125°C 50 100 150 200 250 300 350 400 450 500 550 600 TJ = 25°C VGS = 0 V f = 1 MHz Ciss Coss Crss 0 5 10 15 20 25 30 35 40 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Drain−to−Source Leakage Current versus Voltage Figure 8. Capacitance Variation 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 350 QT 300 250 VDS VGS 200 QGD QGS 150 VDS = 300 V ID = 3 A TJ = 25°C 1 2 3 4 5 6 7 8 9 10 Qg, TOTAL GATE CHARGE (nC) 11 100 50 0 12 45 50 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.10 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 Figure 9. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 1000 10.0 IS, SOURCE CURRENT (A) t, TIME (ns) VDD = 300 V ID = 3 A VGS = 10 V 100 td(off) tr tf td(on) 10.0 1.0 1 10 RG, GATE RESISTANCE (W) TJ = 150°C 1.0 125°C 25°C −55°C 0.1 0.3 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 10. Resistive Switching Time Variation versus Gate Resistance Figure 11. Diode Forward Voltage versus Current www.onsemi.com 4 1.2 NDF03N60Z, NDD03N60Z TYPICAL CHARACTERISTICS 100 VGS v 30 V SINGLE PULSE TC = 25°C 10 100 ms 1 ms 10 ms 1 dc 0.1 0.01 10 ms ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 VGS v 30 V SINGLE PULSE TC = 25°C 10 100 ms 1 ms 10 ms 1 dc 0.1 0.01 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 Figure 12. Maximum Rated Forward Biased Safe Operating Area NDD03N60Z 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 Figure 13. Maximum Rated Forward Biased Safe Operating Area NDF03N60Z 10 R(t) (C/W) 1 50% (DUTY CYCLE) 20% 10% 5.0% 0.1 2.0% 1.0% RqJA = 2°C/W Steady State SINGLE PULSE 0.01 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 PULSE TIME (s) 1E+00 1E+01 1E+02 1E+03 Figure 14. Thermal Impedance (Junction−to−Case) for NDD03N60Z R(t) (C/W) 100 10 50% (DUTY CYCLE) 20% 10% 5.0% 1 2.0% 1.0% 0.1 0.01 1E−06 RqJA = 40°C/W Steady State SINGLE PULSE 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 PULSE TIME (s) Figure 15. Thermal Impedance (Junction−to−Ambient) for NDD03N60Z www.onsemi.com 5 1E+02 1E+03 NDF03N60Z, NDD03N60Z 10 50% (DUTY CYCLE) 1 20% R(t) (C/W) 10% 5.0% 2.0% 0.1 1.0% RqJA = 4.7°C/W Steady State SINGLE PULSE 0.01 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 PULSE TIME (s) 1E+00 1E+01 Figure 16. Thermal Impedance (Junction−to−Case) for NDF03N60Z LEADS HEATSINK 0.110″ MIN Figure 17. Isolation Test Diagram Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 1E+02 1E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 FULLPACK, 3−LEAD CASE 221AH ISSUE F A E B P E/2 0.14 SCALE 1:1 Q D M B A A H1 M A1 C NOTE 3 1 2 3 L L1 3X 3X SEATING PLANE b2 c b 0.25 M B A M C A2 e SIDE VIEW FRONT VIEW SECTION D−D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA­ SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY. 5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00. 6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1 AND H1 FOR MANUFACTURING PURPOSES. MILLIMETERS MIN MAX 4.30 4.70 2.50 2.90 2.50 2.90 0.54 0.84 1.10 1.40 0.49 0.79 14.70 15.30 9.70 10.30 2.54 BSC 6.60 7.10 12.50 14.73 --2.80 3.00 3.40 2.80 3.20 DIM A A1 A2 b b2 c D E e H1 L L1 P Q GENERIC MARKING DIAGRAM* A NOTE 6 DATE 30 SEP 2014 NOTE 6 H1 D D XX XXXXXXXXX AWLYWWG A SECTION A−A ALTERNATE CONSTRUCTION 1 STYLE 1: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE DOCUMENT NUMBER: 98AON52577E DESCRIPTION: A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. TO−220 FULLPACK, 3−LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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