NDF04N60ZG

NDF04N60Z, NDD04N60Z Power MOSFET, N-Channel, 600 V, 2.0 W Features • • • • • Low ON Resistance Low Gate Charge ESD Diode−Protected Gate 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com VDSS (@ TJmax) RDS(on) (MAX) @ 2 A 650 V 2.0 Ω ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Symbol NDF VDSS NDD 600 ID 4.8 4.1 A Continuous Drain Current RqJC, TA = 100°C (Note 1) ID 3.0 2.6 A Pulsed Drain Current, VGS @ 10V IDM 20 20 A Power Dissipation RqJC PD 30 83 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy, ID = 4.0 A EAS 120 mJ ESD (HBM) (JESD22−A114) Vesd 3000 V RMS Isolation Voltage (t = 0.3 sec., R.H. ≤ 30%, TA = 25°C) (Figure 15) VISO Peak Diode Recovery (Note 2) dV/dt 4.5 V/ns MOSFET dV/dt dV/dt 60 V/ns Continuous Source Current (Body Diode) IS 4.0 A Maximum Temperature for Soldering Leads TL 260 °C TJ, Tstg −55 to 150 °C Operating Junction and Storage Temperature Range D (2) V Continuous Drain Current RqJC (Note 1) 4500 N−Channel Unit − G (1) S (3) V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. ISD = 4.0 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C 1 2 3 NDF04N60ZG, NDF04N60ZH TO−220FP CASE 221AH 4 4 1 2 3 NDD04N60Z−1G IPAK CASE 369D 1 2 3 NDD04N60ZT4G DPAK CASE 369AA ORDERING AND MARKING INFORMATION See detailed ordering, marking and shipping information on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2015 May, 2017 − Rev. 10 1 Publication Order Number: NDF04N60Z/D NDF04N60Z, NDD04N60Z THERMAL RESISTANCE Parameter Symbol Value Unit NDF04N60Z NDD04N60Z RqJC 4.2 1.5 °C/W (Note 3) NDF04N60Z (Note 4) NDD04N60Z (Note 3) NDD04N60Z−1 RqJA 50 38 80 Junction−to−Case (Drain) Junction−to−Ambient Steady State 3. Insertion mounted 4. Surface mounted on FR4 board using 1″ sq. pad size (Cu area = 1.127 in sq [2 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Test Conditions Symbol Min Drain−to−Source Breakdown Voltage VGS = 0 V, ID = 1 mA BVDSS 600 Breakdown Voltage Temperature Coefficient Reference to 25°C, ID = 1 mA DBVDSS/ DTJ Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current 25°C VDS = 600 V, VGS = 0 V Gate−to−Source Forward Leakage V 0.6 IDSS V/°C 1 150°C mA 50 VGS = ±20 V IGSS Static Drain−to−Source On−Resistance VGS = 10 V, ID = 2.0 A RDS(on) Gate Threshold Voltage VDS = VGS, ID = 50 mA VGS(th) Forward Transconductance VDS = 15 V, ID = 2.0 A gFS ±10 mA 1.8 2.0 W 3.9 4.5 V ON CHARACTERISTICS (Note 5) 3.0 3.3 S DYNAMIC CHARACTERISTICS Input Capacitance (Note 6) Output Capacitance (Note 6) VDS = 25 V, VGS = 0 V, f = 1.0 MHz Reverse Transfer Capacitance (Note 6) Total Gate Charge (Note 6) Gate−to−Source Charge (Note 6) VDD = 300 V, ID = 4.0 A, VGS = 10 V Gate−to−Drain (“Miller”) Charge Ciss 427 535 640 Coss 50 62 75 Crss 8 14 20 Qg 10 19 29 Qgs 2 3.9 6 Qgd 5 10 15 pF nC nC Plateau Voltage VGP 6.5 V Gate Resistance Rg 4.7 W td(on) 13 ns tr 9.0 td(off) 24 tf 15 RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time VDD = 300 V, ID = 4.0 A, VGS = 10 V, RG = 5 Ω Fall Time SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge IS = 4.0 A, VGS = 0 V VSD VGS = 0 V, VDD = 30 V IS = 4.0 A, di/dt = 100 A/ms trr 285 1.6 ns V Qrr 1.3 mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 6. Guaranteed by design. www.onsemi.com 2 NDF04N60Z, NDD04N60Z TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 8 VGS = 15 V TJ = 25°C 10 V 7V 6 VDS ≥ 30 V ID, DRAIN CURRENT (A) 8 6.8 V 6.6 V 4 6.4 V 6.2 V 6.0 V 2 6 4 TJ = 150°C TJ = 25°C 2 5.8 V 5.6 V 0 5 10 15 20 TJ = −55°C 3 5 7 6 8 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 2 A TJ = 25°C 3 2.5 2 1.5 5 6 7 8 9 10 VGS (V) 3 TJ = 25°C 2.5 2 VGS = 10 V 1.5 1 0.5 1 1.5 2 2.5 3 3.5 4 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.6 10,000 VGS = 0 V ID = 2 A VGS = 10 V 2 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3.5 1 0 25 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 1.4 0.8 TJ = 150°C 1000 100 TJ = 100°C 0.2 −50 −25 0 25 50 75 100 125 150 10 0 100 200 300 400 500 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 600 NDF04N60Z, NDD04N60Z TYPICAL CHARACTERISTICS 800 Ciss 600 Coss 0 Crss 0 50 100 150 200 t, TIME (ns) VDS 5 0 100 TJ = 25°C ID = 4 A 0 5 15 10 tr tf 1 10 0 20 4 td(off) VGS = 0 V TJ = 25°C 3 2 1 0 0.4 100 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 100 VGS ≤ 30 V Single Pulse TC = 25°C 100 ms 1 ms 10 ms dc 10 ms ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 10 1 0.01 0.1 Qgd Figure 7. Capacitance Variation td(on) 0.1 200 Qgs Qg, TOTAL GATE CHARGE (nC) VDD = 300 V ID = 4 A VGS = 10 V 10 300 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 1 QT 15 10 400 200 400 IS, SOURCE CURRENT (A) C, CAPACITANCE (pF) 1000 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 0 V TJ = 25°C f = 1.0 MHz VDS, DRAIN−TO−SOURCE VOLTAGE (V) 20 1200 RDS(on) Limit Thermal Limit Package Limit 1 10 100 1000 1 ms 10 ms 10 10 ms dc 1 VGS ≤ 30 V Single Pulse TC = 25°C 0.1 0.01 100 ms RDS(on) Limit Thermal Limit Package Limit 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area for NDF04N60Z Figure 12. Maximum Rated Forward Biased Safe Operating Area for NDD04N60Z www.onsemi.com 4 1000 NDF04N60Z, NDD04N60Z TYPICAL CHARACTERISTICS 10 R(t) (C/W) 50% (DUTY CYCLE) 1.0 20% 10% 5.0% 0.1 2.0% 1.0% RqJC = 4.2°C/W Steady State SINGLE PULSE 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE TIME (s) Figure 13. Thermal Impedance for NDF04N60Z 10 R(t) (C/W) 1.0 0.1 50% (DUTY CYCLE) 20% 10% 5.0% 2.0% 1.0% 0.01 SINGLE PULSE RqJC = 1.5°C/W Steady State 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 PULSE TIME (s) Figure 14. Thermal Impedance for NDD04N60Z LEADS HEATSINK 0.110″ MIN Figure 15. Mounting Position for Isolation Test Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 100 1000 NDF04N60Z, NDD04N60Z ORDERING INFORMATION Package Shipping† NDF04N60ZG TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDF04N60ZH TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDD04N60Z−1G IPAK (Pb−Free, Halogen−Free) 75 Units / Rail NDD04N60ZT4G DPAK (Pb−Free, Halogen−Free) 2500 / Tape and Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS 4 Drain Source 1 2 3 Gate Drain Source Drain TO−220FP 4 Drain AYWW 4N 60ZG Gate AYWW 4N 60ZG NDF04N60ZG or NDF04N60ZH AYWW 2 1 Drain 3 Gate Source IPAK A Y WW G, H = Location Code* = Year = Work Week = Pb−Free, Halogen−Free Package * The Assembly Location Code (A) is front side optional. In cases where the Assembly Location is stamped in the package bottom (molding ejecter pin), the front side assembly code may be blank. www.onsemi.com 6 DPAK MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 FULLPACK, 3−LEAD CASE 221AH ISSUE F A E B P E/2 0.14 SCALE 1:1 Q D M B A A H1 M A1 C NOTE 3 1 2 3 L L1 3X 3X SEATING PLANE b2 c b 0.25 M B A M C A2 e SIDE VIEW FRONT VIEW SECTION D−D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA­ SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY. 5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00. 6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1 AND H1 FOR MANUFACTURING PURPOSES. MILLIMETERS MIN MAX 4.30 4.70 2.50 2.90 2.50 2.90 0.54 0.84 1.10 1.40 0.49 0.79 14.70 15.30 9.70 10.30 2.54 BSC 6.60 7.10 12.50 14.73 --2.80 3.00 3.40 2.80 3.20 DIM A A1 A2 b b2 c D E e H1 L L1 P Q GENERIC MARKING DIAGRAM* A NOTE 6 DATE 30 SEP 2014 NOTE 6 H1 D D XX XXXXXXXXX AWLYWWG A SECTION A−A ALTERNATE CONSTRUCTION 1 STYLE 1: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE DOCUMENT NUMBER: 98AON52577E DESCRIPTION: A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. TO−220 FULLPACK, 3−LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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