NDF06N60Z
Power MOSFET, N-Channel,
600 V, 1.2 W
Features
•
•
•
•
•
Low ON Resistance
Low Gate Charge
ESD Diode−Protected Gate
100% Avalanche Tested
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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VDSS (@ TJmax)
RDS(ON) (MAX) @ 3 A
650 V
1.2 Ω
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
VDSS
600
V
Continuous Drain Current, RqJC (Note 1)
ID
7.1
A
Continuous Drain Current
TA = 100°C, RqJC (Note 1)
ID
4.5
A
IDM
28
A
Rating
Drain−to−Source Voltage
Pulsed Drain Current,
VGS @ 10 V
Power Dissipation, RqJC
PD
35
W
Gate−to−Source Voltage
VGS
±30
V
Single Pulse Avalanche Energy, L = 6.3 mH,
ID = 6.0 A
EAS
113
mJ
ESD (HBM) (JESD22−A114)
Vesd
3000
V
RMS Isolation Voltage
(t = 0.3 sec., R.H. ≤ 30%,
TA = 25°C) (Figure 13)
VISO
4500
V
Peak Diode Recovery (Note 2)
dv/dt
4.5
V/ns
MOSFET dV/dt
dV/dt
60
V/ns
Continuous Source Current (Body Diode)
IS
6.0
A
Maximum Temperature for Soldering Leads
TL
260
°C
TJ, Tstg
−55 to
150
°C
Operating Junction and
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Limited by maximum junction temperature
2. ISD = 6.0 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8
1
N−Channel
D (2)
G (1)
S (3)
1
2
3
NDF06N60ZG,
NDF06N60ZH
TO−220FP
CASE 221AH
ORDERING AND MARKING INFORMATION
See detailed ordering, marking and shipping information on
page 6 of this data sheet.
Publication Order Number:
NDF06N60Z/D
NDF06N60Z
THERMAL RESISTANCE
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
3.6
°C/W
Junction−to−Ambient Steady State (Note 3)
RqJA
50
3. Insertion mounted
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Test Conditions
Symbol
Min
Drain−to−Source Breakdown Voltage
VGS = 0 V, ID = 1 mA
BVDSS
600
Breakdown Voltage Temperature Coefficient
Reference to 25°C,
ID = 1 mA
DBVDSS/
DTJ
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Leakage Current
V
0.6
V/°C
IDSS
1
VGS = ±20 V
IGSS
±10
mA
Static Drain−to−Source
On−Resistance
VGS = 10 V, ID = 3.0 A
RDS(on)
0.98
1.2
W
Gate Threshold Voltage
VDS = VGS, ID = 100 mA
VGS(th)
3.9
4.5
V
VDS = 15 V, ID = 3.0 A
gFS
VDS = 600 V, VGS = 0 V
Gate−to−Source Forward Leakage
25°C
150°C
mA
50
ON CHARACTERISTICS (Note 4)
Forward Transconductance
3.0
5.0
S
DYNAMIC CHARACTERISTICS
Input Capacitance (Note 5)
Ciss
738
923
1107
Coss
90
106
125
Crss
15
23
30
Total Gate Charge (Note 5)
Qg
15.5
31
47
Gate−to−Source Charge (Note 5)
Qgs
3
6.3
9.5
Qgd
8
17
24.5
Output Capacitance (Note 5)
Reverse Transfer Capacitance
(Note 5)
Gate−to−Drain (“Miller”) Charge
(Note 5)
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
VDD = 300 V, ID = 6.0 A,
VGS = 10 V
pF
nC
Plateau Voltage
VGP
6.4
V
Gate Resistance
Rg
3.2
W
td(on)
13
ns
tr
17
td(off)
30
tf
28
RESISTIVE SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
VDD = 300 V, ID = 6.0 A,
VGS = 10 V, RG = 5 Ω
Fall Time
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted)
Diode Forward Voltage
IS = 6.0 A, VGS = 0 V
VSD
Reverse Recovery Time
VGS = 0 V, VDD = 30 V
IS = 6.0 A, di/dt = 100 A/ms
trr
338
ns
Qrr
2.0
mC
Reverse Recovery Charge
1.6
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%.
5. Guaranteed by design.
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2
NDF06N60Z
TYPICAL CHARACTERISTICS
10
12
6.8 V
VDS ≥ 30 V
6.6 V
VGS = 15 V
8
6.4 V
6
6.2 V
6.0 V
4
5.8 V
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10 V
7V
5.6 V
0
5
10
15
20
8
6
25
TJ = 150°C
4
2
TJ = −55°C
3
6
5
7
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.5
1
0.5
5
6
7
8
9
10
VGS (V)
8
1.75
TJ = 25°C
1.5
1.25
VGS = 10 V
1
0.75
0.5
0
2
4
6
8
10
12
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.6
10,000
VGS = 0 V
ID = 3 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
4
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 3 A
TJ = 25°C
2.2
TJ = 25°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
2
0
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
TJ = 25°C
ID, DRAIN CURRENT (A)
12
1.8
1.4
1.0
TJ = 150°C
1000
100
0.6
TJ = 100°C
0.2
−50
−25
0
25
50
75
100
125
150
10
0
100
200
300
400
500
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
600
NDF06N60Z
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
f = 1 MHz
1500
Crss
0
0
VDS
50
100
150
200
200
Qgs
VGS
0
100
TJ = 25°C
ID = 6 A
0
5
10
15
20
25
30
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
0
35
IS, SOURCE CURRENT (A)
6
VDD = 300 V
ID = 6 A
VGS = 10 V
td(off)
100
tr
tf
td(on)
10
1
10
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
0.4
100
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
Qgd
5
1000
1
300
10
Coss
500
QT
15
Ciss
1000
400
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
20
2000
10
VGS ≤ 30 V
Single Pulse
TC = 25°C
100 ms
1 ms
10 ms
10 ms
dc
1
0.1
0.01
0.1
RDS(on) Limit
Thermal Limit
Package Limit
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area for NDF06N60Z
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4
1000
NDF06N60Z
TYPICAL CHARACTERISTICS
10
R(t) (C/W)
50% (DUTY CYCLE)
1.0
20%
10%
5.0%
2.0%
0.1
1.0%
RqJC = 3.6°C/W
Steady State
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
1.0
10
PULSE TIME (s)
Figure 12. Thermal Impedance for NDF06N60Z
LEADS
HEATSINK
0.110″ MIN
Figure 13. Mounting Position for Isolation Test
Measurement made between leads and heatsink with all leads shorted together.
*For additional mounting information, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
5
100
1000
NDF06N60Z
ORDERING INFORMATION
Package
Shipping†
NDF06N60ZG
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
NDF06N60ZH
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
NDF06N60ZG
or
NDF06N60ZH
AYWW
Gate
Source
Drain
TO−220FP
A
Y
WW
G, H
= Location Code
= Year
= Work Week
= Pb−Free, Halogen−Free Package
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220 FULLPACK, 3−LEAD
CASE 221AH
ISSUE F
A
E
B
P
E/2
0.14
SCALE 1:1
Q
D
M
B A
A
H1
M
A1
C
NOTE 3
1 2 3
L
L1
3X
3X
SEATING
PLANE
b2
c
b
0.25
M
B A
M
C
A2
e
SIDE VIEW
FRONT VIEW
SECTION D−D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR UNCONTROLLED IN THIS AREA.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE
PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO
EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA
SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY.
5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION.
LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00.
6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY
MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1
AND H1 FOR MANUFACTURING PURPOSES.
MILLIMETERS
MIN
MAX
4.30
4.70
2.50
2.90
2.50
2.90
0.54
0.84
1.10
1.40
0.49
0.79
14.70
15.30
9.70
10.30
2.54 BSC
6.60
7.10
12.50
14.73
--2.80
3.00
3.40
2.80
3.20
DIM
A
A1
A2
b
b2
c
D
E
e
H1
L
L1
P
Q
GENERIC
MARKING DIAGRAM*
A
NOTE 6
DATE 30 SEP 2014
NOTE 6
H1
D
D
XX
XXXXXXXXX
AWLYWWG
A
SECTION A−A
ALTERNATE CONSTRUCTION
1
STYLE 1:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. GATE
DOCUMENT NUMBER:
98AON52577E
DESCRIPTION:
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
TO−220 FULLPACK, 3−LEAD
PAGE 1 OF 1
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