NDF08N50ZH

NDF08N50Z N-Channel Power MOSFET 500 V, 0.85 W Features • • • • • Low ON Resistance Low Gate Charge ESD Diode−Protected Gate 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com VDSS RDS(ON) (MAX) @ 3.6 A 500 V 0.85 W ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol NDF08N50Z Unit VDSS 500 V Continuous Drain Current RqJC (Note 1) ID 8.5 A Continuous Drain Current RqJC TA = 100°C (Note 1) ID 5.4 A Pulsed Drain Current, VGS @ 10 V IDM 34 A Power Dissipation PD 35 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy, ID = 7.5 A EAS 190 mJ ESD (HBM) (JESD 22−A114) Vesd 3500 V RMS Isolation Voltage (t = 0.3 sec., R.H. ≤ 30%, TA = 25°C) (Figure 14) VISO 4500 V Peak Diode Recovery (Note 2) dV/dt 4.5 V/ns MOSFET dV/dt dV/dt 60 V/ns Continuous Source Current (Body Diode) IS 7.5 A Maximum Temperature for Soldering Leads TL 260 °C TJ, Tstg −55 to 150 °C Rating Drain−to−Source Voltage Operating Junction and Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature 2. ISD = 7.5 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C N−Channel D (2) G (1) S (3) MARKING DIAGRAM NDF08N50ZG, NDF08N50ZH TO−220FP CASE 221AH Gate January, 2015 − Rev. 6 1 Source Drain A Y WW G, H = Location Code = Year = Work Week = Pb−Free, Halogen−Free Package ORDERING INFORMATION Device Package Shipping NDF08N50ZG TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDF08N50ZH © Semiconductor Components Industries, LLC, 2015 NDF08N50ZG or NDF08N50ZH AYWW TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail Publication Order Number: NDF08N50Z/D NDF08N50Z THERMAL RESISTANCE Symbol NDF08N50Z Unit Junction−to−Case (Drain) Parameter RqJC 3.6 °C/W Junction−to−Ambient Steady State (Note 3) RqJA 50 3. Insertion mounted ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Test Conditions Symbol Min Drain−to−Source Breakdown Voltage VGS = 0 V, ID = 1 mA BVDSS 500 Breakdown Voltage Temperature Coefficient Reference to 25°C, ID = 1 mA DBVDSS/ DTJ Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current Gate−to−Source Forward Leakage 0.6 IDSS 25°C VDS = 500 V, VGS = 0 V V V/°C 1 150°C mA 50 VGS = ±20 V IGSS Static Drain−to−Source On−Resistance VGS = 10 V, ID = 3.6 A RDS(on) Gate Threshold Voltage VDS = VGS, ID = 100 mA VGS(th) Forward Transconductance VDS = 15 V, ID = 3.75 A gFS ±10 mA 0.69 0.85 W 3.9 4.5 V ON CHARACTERISTICS (Note 4) 3.0 6.0 S DYNAMIC CHARACTERISTICS Input Capacitance (Note 5) Output Capacitance (Note 5) VDS = 25 V, VGS = 0 V, f = 1.0 MHz Reverse Transfer Capacitance (Note 5) Total Gate Charge (Note 5) Gate−to−Source Charge (Note 5) VDD = 250 V, ID = 7.5 A, VGS = 10 V Gate−to−Drain (“Miller”) Charge (Note 5) Ciss 730 912 1095 Coss 95 120 140 Crss 15 27 35 Qg 16 31 46 Qgs 3 6.2 9 Qgd 8 17 25 pF nC Plateau Voltage VGP 6.3 V Gate Resistance Rg 3.0 W td(on) 13 ns tr 23 td(off) 31 tf 29 RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time VDD = 250 V, ID = 7.5 A, VGS = 10 V, RG = 5 W Fall Time SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage IS = 7.5 A, VGS = 0 V VSD Reverse Recovery Time VGS = 0 V, VDD = 30 V IS = 7.5 A, di/dt = 100 A/ms trr 295 ns Qrr 1.85 mC Reverse Recovery Charge 1.6 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 5. Guaranteed by design. www.onsemi.com 2 NDF08N50Z TYPICAL CHARACTERISTICS 20.0 20.0 16.0 14.0 7.0 V VGS = 10 V 12.0 6.5 V 10.0 8.0 6.0 V 6.0 4.0 5.5 V 2.0 5.0 10.0 15.0 16.0 14.0 12.0 10.0 8.0 TJ = 25°C 6.0 TJ = 150°C 4.0 20.0 0.0 25.0 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.85 0.80 0.75 0.70 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10 2.25 7 8 9 10 1.00 0.95 0.90 VGS = 10 V TJ = 25°C 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.75 2.50 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.90 ID = 3.6 A VGS = 10 V 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = 3.6 A TJ = 25°C 6.0 6 Figure 2. Transfer Characteristics 1.00 0.65 5.5 5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics 0.95 TJ = −55°C 2.0 5.0 V 0.0 0.0 VDS = 25 V 18.0 8.0 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 18.0 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 Figure 5. On−Resistance Variation with Temperature −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 6. BVDSS Variation with Temperature www.onsemi.com 3 10 150 NDF08N50Z TYPICAL CHARACTERISTICS 2000 10 TJ = 25°C VGS = 0 V f = 1 MHz 1800 C, CAPACITANCE (pF) 1.0 TJ = 125°C 1600 1400 1200 Ciss 1000 800 600 400 200 0 50 0 100 150 200 250 300 350 400 450 500 0 5 10 15 20 25 30 35 40 45 50 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.2 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Drain−to−Source Leakage Current versus Voltage Figure 8. Capacitance Variation VGS, GATE−TO−SOURCE VOLTAGE (V) 0.10 Coss Crss 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 300 QT 250 200 VDS VGS 150 QGD QGS 100 VDS = 250 V ID = 7.5 A TJ = 25°C 0 4 8 12 16 20 24 28 50 0 32 VDS, DRAIN−TO−SOURCE VOLTAGE (V) IDSS, LEAKAGE (mA) TJ = 150°C Qg, TOTAL GATE CHARGE (nC) Figure 9. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 1000 t, TIME (ns) VDD = 250 V ID = 7.5 A VGS = 10 V 100 IS, SOURCE CURRENT (A) 10.0 td(off) tr tf td(on) 10 1.0 1 10 RG, GATE RESISTANCE (W) 100 TJ = 150°C 1.0 125°C 25°C −55°C 0.1 0.3 Figure 10. Resistive Switching Time Variation versus Gate Resistance Figure 11. Diode Forward Voltage versus Current www.onsemi.com 4 NDF08N50Z TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 100 VGS v 30 V SINGLE PULSE TC = 25°C 10 100 ms 1 ms 10 ms 10 ms dc 1 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 Figure 12. Maximum Rated Forward Biased Safe Operating Area NDF08N50Z 10 R(t) (C/W) 50% (DUTY CYCLE) 1 20% 10% 5.0% 0.1 2.0% 1.0% 0.01 0.000001 RqJC = 3.6°C/W Steady State SINGLE PULSE 0.00001 0.0001 0.001 0.01 0.1 1.0 10 PULSE TIME (s) Figure 13. Thermal Impedance (Junction−to−Case) for NDF08N50Z LEADS HEATSINK 0.110″ MIN Figure 14. Isolation Test Diagram Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 FULLPACK, 3−LEAD CASE 221AH ISSUE F A E B P E/2 0.14 SCALE 1:1 Q D M B A A H1 M A1 C NOTE 3 1 2 3 L L1 3X 3X SEATING PLANE b2 c b 0.25 M B A M C A2 e SIDE VIEW FRONT VIEW SECTION D−D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA­ SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY. 5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00. 6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1 AND H1 FOR MANUFACTURING PURPOSES. MILLIMETERS MIN MAX 4.30 4.70 2.50 2.90 2.50 2.90 0.54 0.84 1.10 1.40 0.49 0.79 14.70 15.30 9.70 10.30 2.54 BSC 6.60 7.10 12.50 14.73 --2.80 3.00 3.40 2.80 3.20 DIM A A1 A2 b b2 c D E e H1 L L1 P Q GENERIC MARKING DIAGRAM* A NOTE 6 DATE 30 SEP 2014 NOTE 6 H1 D D XX XXXXXXXXX AWLYWWG A SECTION A−A ALTERNATE CONSTRUCTION 1 STYLE 1: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE DOCUMENT NUMBER: 98AON52577E DESCRIPTION: A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. TO−220 FULLPACK, 3−LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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