NDF10N60ZG

NDF10N60Z N-Channel Power MOSFET 600 V, 0.75 W Features • • • • • • Low ON Resistance Low Gate Charge ESD Diode−Protected Gate 100% Avalanche Tested 100% Rg Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com VDSS (@ TJmax) RDS(ON) (MAX) @ 5 A 650 V 0.75 W ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol NDF Unit VDSS 600 V Continuous Drain Current, RqJC (Note 1) ID 10 A Continuous Drain Current TA = 100°C, RqJC (Note 1) ID 6.0 A Pulsed Drain Current, tP = 10 ms IDM 40 A Power Dissipation, RqJC PD 39 W Gate−to−Source Voltage VGS ±30 V Single Pulse Avalanche Energy (L = 6.0 mH, ID = 10 A) EAS 300 mJ ESD (HBM) (JESD22−A114) Vesd 3900 V RMS Isolation Voltage (t = 0.3 sec., R.H. ≤ 30%, TA = 25°C) (Figure 13) VISO 4500 V Peak Diode Recovery (Note 2) dV/dt 4.5 V/ns MOSFET dV/dt dV/dt 60 V/ns Continuous Source Current (Body Diode) IS 10 A Maximum Temperature for Soldering Leads TL 260 °C Operating Junction and Storage Temperature Range TJ, Tstg −55 to 150 °C Rating Drain−to−Source Voltage Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Limited by maximum junction temperature. 2. IS ≤ 10 A, di/dt ≤ 200 A/ms, VDD = 80% BVDSS © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 13 1 N−Channel D (2) G (1) S (3) 1 2 3 NDF10N60ZG NDF10N60ZH TO−220FP CASE 221AH ORDERING AND MARKING INFORMATION See detailed ordering, marking and shipping information on page 6 of this data sheet. Publication Order Number: NDF10N60Z/D NDF10N60Z THERMAL RESISTANCE Symbol NDF10N60Z Unit Junction−to−Case (Drain) Parameter RqJC 3.2 °C/W Junction−to−Ambient Steady State (Note 3) RqJA 50 3. Insertion mounted ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Test Conditions Symbol Min VGS = 0 V, ID = 1 mA BVDSS 600 Reference to 25°C, ID = 1 mA DBVDSS/ DTJ Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Drain−to−Source Leakage Current V 0.6 V/°C IDSS 1 VGS = ±20 V IGSS ±10 mA Static Drain−to−Source On−Resistance VGS = 10 V, ID = 5.0 A RDS(on) 0.65 0.75 W Gate Threshold Voltage VDS = VGS, ID = 100 mA VGS(th) 3.9 4.5 V VDS = 15 V, ID = 10 A gFS VDS = 600 V, VGS = 0 V Gate−to−Source Forward Leakage 25°C 150°C mA 50 ON CHARACTERISTICS (Note 4) Forward Transconductance 3.0 7.9 S DYNAMIC CHARACTERISTICS Input Capacitance (Note 5) Ciss 1097 1373 1645 Coss 118 150 178 Reverse Transfer Capacitance (Note 5) Crss 20 35 50 Total Gate Charge (Note 5) Qg 23 47 68 Qgs 5.0 9.0 14 Qgd 12 26 36 Output Capacitance (Note 5) Gate−to−Source Charge (Note 5) Gate−to−Drain (“Miller”) Charge (Note 5) VDS = 25 V, VGS = 0 V, f = 1.0 MHz VDD = 300 V, ID = 10 A, VGS = 10 V Plateau Voltage VGP Gate Resistance Rg 6.4 0.5 1.5 pF nC V 4.5 W RESISTIVE SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time VDD = 300 V, ID = 10 A, VGS = 10 V, RG = 5 Ω Fall Time td(on) 15 tr 31 td(off) 40 tf 23 ns SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage IS = 10 A, VGS = 0 V VSD Reverse Recovery Time VGS = 0 V, VDD = 30 V IS = 10 A, di/dt = 100 A/ms trr 395 ns Qrr 3.0 mC Reverse Recovery Charge 1.6 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. 5. Guaranteed by design. www.onsemi.com 2 NDF10N60Z TYPICAL CHARACTERISTICS 20 7.0 V 14 6.4 V 12 6.2 V 10 6.0 V 8 5.8 V 6 5.6 V 5.4 V 4 4 8 12 16 20 24 14 12 10 8 TJ = 150°C 6 4 TJ = −55°C 2 5 6 7 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.75 0.70 ID = 5 A 0.65 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 8 0.80 TJ = 25°C VGS = 10 V 0.75 0.70 0.65 0.60 2.5 5.0 7.5 10 12.5 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 2.7 VGS = 0 V VGS = 10 V ID = 5 A IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 25°C 2.2 3 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.80 0.60 TJ = 25°C 16 2 0 5.0 V 0 VDS = 30 V 18 6.6 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 10 V 16 2 0 20 VGS = 15 V TJ = 25°C ID, DRAIN CURRENT (A) 18 TJ = 150°C 1000 1.7 1.2 100 TJ = 100°C 0.7 0.2 −50 −25 0 25 50 75 100 125 150 10 0 100 200 300 400 500 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 600 NDF10N60Z TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 0 V TJ = 25°C f = 1 MHz 3000 2500 2000 Ciss 1500 1000 Crss 500 0 Coss 0 25 50 75 100 125 150 175 20 400 ID = 10 A TJ = 25°C 15 300 VDS QT 10 200 Qgs Qgd 0 0 5 10 IS, SOURCE CURRENT (A) tr tf td(on) 10 25 30 35 40 45 50 0 55 8 6 4 2 0 100 VGS = 0 V TJ = 25°C 0.4 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Source Current vs. Forward Voltage 100 ID, DRAIN CURRENT (A) t, TIME (ns) 10 VDD = 300 V ID = 10 A VGS = 10 V 1 20 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge td(off) 10 15 100 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 100 VGS 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 200 10 100 ms 10 ms VGS ≤ 30 V Single Pulse TC = 25°C 1 ms 10 ms dc 1 0.1 0.01 0.1 RDS(on) Limit Thermal Limit Package Limit 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3500 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area for NDF10N60Z www.onsemi.com 4 1000 1.0 NDF10N60Z TYPICAL CHARACTERISTICS 10 R(t) (°C/W) Duty Cycle = 50% 1 20% 10% 5% 0.1 2% 1% 0.01 RqJC = 3.2°C/W Steady State Single Pulse 0.001 0.000001 0.00001 0.0001 0.001 0.1 0.01 1 10 PULSE TIME (sec) Figure 12. Thermal Impedance for NDF10N60Z LEADS HEATSINK 0.110″ MIN Figure 13. Mounting Position for Isolation Test Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 100 1000 NDF10N60Z ORDERING INFORMATION Package Shipping† NDF10N60ZG TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail NDF10N60ZH TO−220FP (Pb−Free, Halogen−Free) 50 Units / Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS NDF10N60ZG or NDF10N60ZH AYWW Gate Source Drain TO−220FP A Y WW G, H = Location Code = Year = Work Week = Pb−Free, Halogen−Free Package www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 FULLPACK, 3−LEAD CASE 221AH ISSUE F A E B P E/2 0.14 SCALE 1:1 Q D M B A A H1 M A1 C NOTE 3 1 2 3 L L1 3X 3X SEATING PLANE b2 c b 0.25 M B A M C A2 e SIDE VIEW FRONT VIEW SECTION D−D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA­ SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY. 5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00. 6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1 AND H1 FOR MANUFACTURING PURPOSES. MILLIMETERS MIN MAX 4.30 4.70 2.50 2.90 2.50 2.90 0.54 0.84 1.10 1.40 0.49 0.79 14.70 15.30 9.70 10.30 2.54 BSC 6.60 7.10 12.50 14.73 --2.80 3.00 3.40 2.80 3.20 DIM A A1 A2 b b2 c D E e H1 L L1 P Q GENERIC MARKING DIAGRAM* A NOTE 6 DATE 30 SEP 2014 NOTE 6 H1 D D XX XXXXXXXXX AWLYWWG A SECTION A−A ALTERNATE CONSTRUCTION 1 STYLE 1: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE DOCUMENT NUMBER: 98AON52577E DESCRIPTION: A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. TO−220 FULLPACK, 3−LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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