NDS336P

June 1997 NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features SuperSOTTM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. -1.2 A, -20 V, RDS(ON) = 0.27 Ω @ VGS= -2.7 V RDS(ON) = 0.2 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface package. Mount ________________________________________________________________________________ D S G Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter NDS336P Units VDSS Drain-Source Voltage -20 V VGSS Gate-Source Voltage - Continuous ±8 V ID Maximum Drain Current - Continuous -1.2 A (Note 1a) - Pulsed PD Maximum Power Dissipation -10 (Note 1a) (Note 1b) TJ,TSTG Operating and Storage Temperature Range 0.5 W 0.46 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W © 1997 Fairchild Semiconductor Corporation NDS336P Rev. E Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -20 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V V TJ =55°C -1 µA -10 µA IGSS Gate - Body Leakage Current VGS = 8 V, VDS = 0 V 100 nA IGSS Gate - Body Leakage Current VGS = -8 V, VDS = 0 V -100 nA -1 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA RDS(ON) Static Drain-Source On-Resistance VGS = -2.7 V, ID = -1.2 A TJ =125°C -0.5 -0.78 -0.3 -0.58 -0.8 0.22 0.27 0.34 0.49 0.16 0.2 TJ =125°C VGS = -4.5 V, ID = -1.3 A -2 Ω ID(ON) On-State Drain Current VGS = -2.7 V, VDS = -5 V gFS Forward Transconductance VDS = -5 V, ID = -1.2 A -3 A S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 360 pF 170 pF 60 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) tf Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -5 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 Ω 8 15 ns 29 50 ns Turn - Off Delay Time 33 60 ns Turn - Off Fall Time 23 45 ns 5.7 8.5 nC VDS = -10 V, ID = -1.2 A, VGS = -4.5 V 0.7 nC 1.8 nC NDS336P Rev. E Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -0.42 A -10 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 (Note 2) -0.65 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solde mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t) = T J −T A R θJA(t) = T J −T A R θJC +R θCA(t) = I 2D (t) × R DS(ON)@T J Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS336P Rev. E Typical Electrical Characteristics V GS = -4.5V 2 -4.0 -8 -3.5 -6 R DS(on) , NORMALIZED -3.0 -2.7 -2.5 -4 -2.0 -2 0 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) -10 1.8 -2.5 1.4 -1 -2 V DS -3 -4 -2.7 -3.0 1.2 -3.5 1 -4.0 -4.5 0.8 0.6 0 V GS=-2.0V 1.6 -5 0 -2 Figure 1. On-Region Characteristics. -8 -10 1.4 R DS(on) , NORMALIZED GS 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE 2 ID = -1.2A V = -2.7V VGS = -2.7V 1.8 1.6 TJ = 125°C 1.4 25°C 1.2 -55°C 1 0.8 0.6 150 0 -2 -4 -6 I , DRAIN CURRENT (A) -8 -10 D Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. -5 T = -55°C J -25°C -4 -125°C -3 -2 -1 0 -0.5 -1 -1.5 V GS -2 -2.5 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -3 GATE-SOURCE THRESHOLD VOLTAGE 1.2 V DS = -5V VGS(th) , NORMALIZED R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -6 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 I D , DRAIN CURRENT (A) -4 I D , DRAIN CURRENT (A) , DRAIN-SOURCE VOLTAGE (V) VDS = VGS I D = -250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS336P Rev. D Typical Electrical Characteristics (continued) 5 I D = - 250µA -I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.06 1.04 1.02 1 0.98 0.96 -50 -25 0 T J 25 50 75 100 125 150 V GS = 0V 1 T J = 125°C 0.1 25°C 0.001 0.0001 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) , JUNCTION TEMPERATURE (°C) 800 -VGS , GATE-SOURCE VOLTAGE (V) 5 500 Ciss 300 200 Coss 100 f = 1 MHz V GS = 0V 60 40 0.1 Crss VDS = -5V I D = -1.2A -10V 4 -15V 3 2 1 0 0.2 0.5 1 2 5 -VDS , DRAIN TO SOURCE VOLTAGE (V) 10 0 20 2 6 8 Figure 10. Gate Charge Characteristics. VDD ton t d(on) t off tr RL VIN 4 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. t d(off) tf 90% 90% V OUT D VGS 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. Figure 7. Breakdown Voltage Variation with Temperature. CAPACITANCE (pF) -55°C 0.01 VOUT R GEN 10% 10% DUT G 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. INVERTED Figure 12. Switching Waveforms. NDS336P Rev. D 20 8 V DS= -5V 6 -25°C -125°C 4 2 0 0 -2 -4 -6 -8 -10 5 2 R 1 (O DS N) 0.05 0.01 0.1 0.2 0.5 -ID , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 0.8 1a 1b 0.4 4.5"x5" FR-4 Board o TA = 25 C Still Air 0 0.2 1 2 5 10 20 30 Figure 14. Maximum Safe Operating Area. 1 0.1 10m s 100 ms 1s DC -V DS , DRAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature. 0 IT V GS = -2.7V SINGLE PULSE RθJA = See Note 1b TA = 25°C 0.1 D 0.2 LIM 0.5 I , DRAIN CURRENT (A) 0.6 100 us 1m s 10 TJ = -55°C -I D , DRAIN CURRENT (A) gFS, TRANSCONDUCTANCE (SIEMENS) Typical Electrical Characteristics (continued) 0.3 1.6 1.4 1.2 1a 1b 4.5"x5" FR-4 Board o TA = 25 C Still Air VGS = -2.7V 1 0.8 0.4 0 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in2 ) 2oz COPPER MOUNTING PAD AREA (in2 ) Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 0.2 D = 0.5 R θJA (t) = r(t) * R θJA R θJA = See Note 1b 0.2 0.1 0.1 0.05 0.05 0.02 0.01 0.005 P(pk) 0.02 t1 0.01 t2 TJ - TA = P * R θJA (t) Single Pulse Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDS336P Rev. D TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4