NDS8435A

March 1997 NDS8435A Single P-Channel Enhancement Mode Field Effect Transistor General Description Features SO-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -7.9 A, -30 V. RDS(ON) = 0.023 Ω @ VGS = -10 V RDS(ON) = 0.035 Ω @ VGS = -4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ___________________________________________________________________________________________ Absolute Maximum Ratings 5 4 6 3 7 2 8 1 T A = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage -30 V VGSS Gate-Source Voltage ±20 V ID Drain Current - Continuous - Pulsed (Note 1a) -7.9 A Maximum Power Dissipation (Note 1a) 2.5 (Note 1b) 1.2 PD NDS8435A -25 (Note 1c) TJ,TSTG Units Operating and Storage Temperature Range W 1 -55 to 150 °C (Note 1a) 50 °C/W (Note 1) 25 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case © 1997 Fairchild Semiconductor Corporation NDS8435A Rev.C1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -30 Typ Max Units -1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V V -10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V TJ = 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ = 125°C RDS(ON) Static Drain-Source On-Resistance -1 -1.3 -3 -0.7 -1 -2.2 VGS = -10 V, ID = -7.9 A TJ = 125°C VGS = -4.5 V, ID = -6.5 A ID(on) On-State Drain Current gFS Forward Transconductance VGS = -10 V, VDS = -5 V -25 VGS = -4.5, VDS = -5 V -10 0.02 0.023 0.027 0.041 0.03 0.035 Ω A VDS = -10 V, ID = -7.9 A -17 S VDS = -15 V, VGS = 0 V, f = 1.0 MHz 1800 pF 950 pF 240 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time 11 22 ns 20 35 ns tD(off) tf Turn - Off Delay Time 95 180 ns Turn - Off Fall Time 46 100 ns Qg Total Gate Charge Qgs Gate-Source Charge 48 67 nC Qgd Gate-Drain Charge VDD = -10 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω VDS = -15 V, ID = -7.9 A, VGS = -10 V 6 nC 12 nC NDS8435A Rev.C1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -2.1 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A -0.74 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD(t ) = T J −TA R θJA(t ) = T J −TA R θJC+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8435A Rev.C1 Typical Electrical Characteristics 2.5 V GS =-10V -6.0 -4.5 -4.0 -24 R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) -30 -3.5 -18 -3.0 -12 -6 0 -2.5 0 -0.5 -1 -1.5 -2 -2.5 GS =-3.5V -4.0 -4.5 1.5 -5.0 -6.0 -7.0 -10 1 0.5 -3 V 2 0 -5 -10 -15 ID , DRAIN CURRENT (A) VDS , DRAIN-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics. R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 2 I D = -7.9A V GS = -10V 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 VGS = -10V 25°C 1 -55°C 0.5 0 150 TJ = 125°C 1.5 0 -5 -10 I J V DS = -10V V GS(th) , NORMALIZED I D , DRAIN CURRENT (A) 25°C 125°C -20 -15 -10 -5 -1.5 -2 -2.5 -3 -3.5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Charateristics. -15 -20 -25 , DRAIN CURRENT (A) 1.2 T J = -55°C -4 GATE-SOURCE THRESHOLD VOLTAGE -25 D Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. -1 -25 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 0 -20 VDS = VGS I D =-250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 150 J Figure 6. Gate Threshold Variation with Temperature. NDS8435A Rev.C1 Typical Electrical Characteristics (continued) 1.1 20 ID = -250µA 1.075 1.05 1.025 1 0.95 0.925 -50 25°C 0.1 -55°C 0.01 0.001 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 0.0001 150 Figure 7. Breakdown Voltage Variation with Temperature. I Ciss 1000 Coss -V GS, GATE-SOURCE VOLTAGE (V) CAPACITANCE (pF) 2000 500 f = 1 MHz Crss V GS = 0 V 0 .2 -V 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) DS 20 1.2 -10 -15 4 2 0 10 ton t d(on) t d(off) 90% V OUT VOUT 10% 10% DUT 90% V IN S 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. 50 tf 90% D G 40 t off tr RL V IN 20 30 Q g , GATE CHARGE (nC) Figure 10. Gate Charge Characteristics. -VDD R GEN V DS = -5V = -7.9A 6 0 30 D 8 Figure 9. Capacitance Characteristics. VGS 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 10 3000 150 0 .1 0 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 4000 300 TJ = 125°C 1 S 0.975 VGS = 0V 5 -I , REVERSE DRAIN CURRENT (A) BV DSS, NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.125 INVERTED Figure 12. Switching Waveforms. NDS8435A Rev.C1 2.5 40 V DS = - 10V STEADY-STATE POWER DISSIPATION (W) gFS , TRANSCONDUCTANCE (SIEMENS) Typical Electrical and ThermalCharacteristics (continued) TJ = -55°C 32 25°C 24 125°C 16 8 0 0 -6 -12 -18 -24 -30 1a 2 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) ID , DRAIN CURRENT (A) Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 50 30 1a 10 7.5 -I D, DRAIN CURRENT (A) -I D , STEADY-STATE DRAIN CURRENT (A) 8.5 8 7 6.5 1b 6 4.5"x5" FR-4 Board 1c o TA = 2 5 C 5.5 S RD (O 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) Figure 15. Maximum Steady- State Drain Current versus Copper Mounting Pad Area. 10 IT 1m 10 10 1 0.01 0.1 s s 10 s DC VGS = -10V 0.1 0.05 0u s ms 0m 1s 0.5 SINGLE PULSE R θJ A A 1 LIM 2 Still Air 0 N) 5 VG S = - 1 0 V 5 1 0.2 = See Note 1c TA = 25°C 0.5 1 2 5 10 - V DS , DRAIN-SOURCE VOLTAGE (V) 20 30 50 Figure 16. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 0.2 0.1 0.05 0.02 D = 0.5 0.2 R θJA (t) = r(t) * R θJA R θJA = See note 1c 0.1 0.05 0.02 P(pk) 0.01 t1 0.01 Single Pulse 0.005 (t) θJA Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 t2 TJ - TA = P * R 0.001 0.01 0.1 t1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8435A Rev.C1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.