NDS8961

June 1997 NDS8961 Dual N-Channel Enhancement Mode Field Effect Transistor General Description Features SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance.These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 3.1 A, 30 V. RDS(ON) = 0.1 Ω @ VGS = 10 V RDS(ON) = 0.15 Ω @ VGS = 4.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. ____________________________________________________________________________________________ 5 4 6 3 7 2 8 1 Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter NDS8961 Units VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage ±20 V ID Drain Current - Continuous 3.1 A PD Power Dissipation for Dual Operation (Note 1a) - Pulsed Power Dissipation for Single Operation TJ,TSTG 10 2 (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W © 1997 Fairchild Semiconductor Corporation NDS8961 Rev.D ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V TJ = 55oC 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ = 125oC RDS(ON) Static Drain-Source On-Resistance 1 1.6 3 0.7 1.2 2 VGS = 10 V, ID = 3.1 A TJ = 125oC VGS = 4.5 V, ID = 2.6 A ID(on) gFS On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V 10 VGS = 4.5 V, VDS = 5 V 4 0.072 0.1 0.107 0.18 0.116 0.15 Ω A VDS = 10 V, ID = 3.1 A 4.3 S VDS= 15 V, VGS = 0 V, f = 1.0 MHz 190 pF 120 pF 40 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω VDS = 10 V, ID = 3.1 A, VGS = 10 V 7 15 ns 15 30 ns 14 28 ns 3 6 ns 7.1 10 nC 1.2 nC 1.9 nC NDS8961 Rev.D ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1.3 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A 0.79 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J − TA R θJA(t ) = T J −TA R θJC+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8961 Rev.D Typical Electrical Characteristics 10 2.5 5.0 VGS = 3.5V 4.5 8 4.0 6 4 3.5 2 0 3.0 0 0.5 1 1.5 2 V DS , DRAIN-SOURCE VOLTAGE (V) 2.5 DRAIN-SOURCE ON-RESISTANCE 6.0 R DS(on), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) V GS =10V 2 4.5 5.0 1.5 5.5 0 1 .8 2 V GS R DS(on), NORMALIZED V GS = 10V 1 .4 1 .2 1 0 .8 -25 0 25 50 75 100 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1 .6 0 .6 -50 4 6 ID , DRAIN CURRENT (A) 8 10 2 25°C 1 -55°C 0.5 0 150 T = 125°C J 1.5 0 2 I J D Figure 3. On-Resistance Variation with Temperature. 10 V th, NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE 25°C 125°C 6 4 2 3 V GS 8 10 1.2 8 2 4 6 , DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Drain Current and Temperature. T = -55°C J V DS = 10V D 10 = 10V T , JUNCTION TEMPERATURE (°C) I , DRAIN CURRENT (A) 8.0 2.5 ID = 3.1A 1 7.0 Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. Figure 1. On-Region Characteristics. 0 6.0 1 0.5 3 4.0 4 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 5 6 VDS = VGS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 150 J Figure 6. Gate Threshold Variation with Temperature. NDS8961 Rev.D Typical Electrical Characteristics 10 5 I D = 250µA VGS =0V I , REVERSE DRAIN CURRENT (A) 1.08 1.04 1 0.96 1 TJ = 125°C 0 .1 25°C 0 .0 1 -55°C 0 .0 0 1 S BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 0.92 -50 -25 0 T J 25 50 75 100 , JUNCTION TEMPERATURE (°C) 125 150 0 .0 0 0 1 0 SD 0 .4 0.6 0 .8 1 , BODY DIODE FORWARD VOLTAGE (V) 600 10 V DS = 5V I D = 3.1A 200 , GATE-SOURCE VOLTAGE (V) 400 Ciss Coss 100 70 50 Crss f = 1 MHz 20 0 .1 8 0 .2 V 6 4 2 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 30 0 0 2 g 6 t on VDD t d(on) RL t off tr t d(off) tf 90% 90% V OUT D 8 , GATE CHARGE (nC) Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. V IN 4 Q DS R GEN 10V 15V V GS V GS = 0 V 30 VGS 1 .2 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. Figure 7. Breakdown Voltage Variation with Temperature. CAPACITANCE (pF) 0 .2 V VOUT 10% 10% DUT G INVERTED 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDS8961 Rev.D Typical Electrical and Thermal Characteristics STEADY-STATE POWER DISSIPATION (W) 8 TJ = -55°C 6 25°C 4 125°C 2 g FS , TRANSCONDUCTANCE (SIEMENS) V DS = 10V 0 0 2 I D 4 6 , DRAIN CURRENT (A) 8 2.5 1a 1.5 Power for Single Operation 1b 1c 1 0.5 10 0 0.2 0.4 0.6 0.8 1 Figure 14. SO-8 Dual Package Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 3.5 30 1a 10 10 3 I D , DRAIN CURRENT (A) 5 1b 2.5 1c 2 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 1.5 RD 0 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in 2 ) S(O LI N) 1m T MI 10 10 1 1s 0.5 10 0m 0u s s ms s s DC V GS = 10V 0.1 SINGLE PULSE 0.05 R θJ A = See Note 1c VG S = 1 0 V 1 4.5"x5" FR-4 Board o TA = 25 C Still Air 2oz COPPER MOUNTING PAD AREA (in2 ) Figure 13. Transconductance Variation with Drain Current and Temperature. TA = 25°C 0.01 0.1 0.5 0.2 0.5 V DS 1 2 5 10 20 30 50 , DRAIN-SOURCE VOLTAGE (V) Figure 16. Maximum Safe Operating Area. Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE I D, STEADY-STATE DRAIN CURRENT (A) Total Power for Dual Operation 2 0 .5 D = 0.5 0 .2 0.2 0 .1 0 .0 5 0 .0 2 0 .0 1 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.1 0.05 P(pk) 0.02 0.01 t1 Single Pulse 0 .0 0 5 = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 A 0 .0 0 2 0 .0 0 1 0 .0001 t2 TJ - T 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8961 Rev.D SO-8 Tape and Reel Data and Package Dimensions SOIC(8lds) Packaging Configuration: Figure 1.0 Packaging Description: EL ECT ROST AT IC SEN SIT IVE DEVICES DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms Antistatic Cover Tape ESD Label SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. Static Dissipative Embossed Carrier Tape F63TNR Label Customized Label F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 Pin 1 SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Standard (no flow code) TNR 2,500 L86Z F011 D84Z Rail/Tube TNR TNR 95 4,000 500 13" Dia - 13" Dia 7" Dia 343x64x343 530x130x83 343x64x343 184x187x47 Max qty per Box 5,000 30,000 8,000 1,000 Weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 Weight per Reel (kg) 0.6060 - 0.9696 0.1182 Reel Size Box Dimension (mm) SOIC-8 Unit Orientation Note/Comments 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample F63TNLabel F63TN Label LOT: CBVK741B019 QTY: 2500 FSID: FDS9953A SPEC: D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F ESD Label (F63TNR)3 SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0 P0 D0 T E1 F K0 Wc W E2 B0 Tc A0 D1 P1 User Direction of Feed Dimensions are in millimeter Pkg type A0 B0 SOIC(8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 W 12.0 +/-0.3 D0 D1 E1 E2 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 F 10.25 min 5.50 +/-0.05 P1 P0 8.0 +/-0.1 4.0 +/-0.1 K0 2.1 +/-0.10 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). T Wc 0.450 +/0.150 9.2 +/-0.3 0.06 +/-0.02 0.5mm maximum 20 deg maximum Typical component cavity center line B0 Tc 0.5mm maximum 20 deg maximum component rotation Typical component center line Sketch A (Side or Front Sectional View) A0 Component Rotation Sketch C (Top View) Component lateral movement Sketch B (Top View) SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max See detail AA Dim N 7" Diameter Option B Min Dim C See detail AA W3 13" Diameter Option Dim D min W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size Reel Option Dim A Dim B 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 12mm 7" Dia 7.00 177.8 12mm 13" Dia 13.00 330  1998 Fairchild Semiconductor Corporation Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL) July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC-8 (FS PKG Code S1) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0774 9 September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. D