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February 1996
NDS9952A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These dual N- and P-channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
N-Channel 3.7A, 30V, RDS(ON)=0.08Ω @ VGS=10V.
P-Channel -2.9A, -30V, RDS(ON)=0.13Ω @ VGS=-10V.
High density cell design or extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
________________________________________________________________________________
Absolute Maximum Ratings
Symbol
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain Current - Continuous
(Note 1a)
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
TJ,TSTG
4
6
3
7
2
8
1
T A= 25°C unless otherwise noted
- Pulsed
PD
5
N-Channel
P-Channel
Units
30
-30
V
± 20
± 20
V
± 3.7
± 2.9
A
± 15
± 10
2
(Note 1a)
(Note 1b)
1
(Note 1c)
0.9
Operating and Storage Temperature Range
W
1.6
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
40
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS9952A.SAM
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Type
Min
N-Ch
30
-30
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = -250 µA
P-Ch
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
N-Ch
V
V
TJ = 55°C
VDS = -24 V, VGS = 0 V
2
µA
25
µA
P-Ch
-2
µA
-25
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
All
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
All
-100
nA
V
TJ = 55°C
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
N-Ch
TJ = 125°C
P-Ch
VDS = VGS, ID = -250 µA
TJ = 125°C
RDS(ON)
Static Drain-Source On-Resistance
1
1.7
2.8
0.7
1.2
2.2
-1
-1.6
-2.8
-0.85
-1.25
-2.5
0.06
0.08
0.08
0.13
0.08
0.11
N-Ch
VGS = 10 V, ID = 1.0 A
TJ = 125°C
VGS = 4.5 V, ID = 0.5 A
TJ = 125°C
P-Ch
VGS = -10 V, ID = -1.0 A
TJ = 125°C
VGS = -4.5 V, ID = -0.5 A
TJ = 125°C
ID(on)
On-State Drain Current
VGS = 10 V, VDS = 5 V
gFS
Forward Transconductance
0.11
0.18
0.11
0.13
0.15
0.21
0.17
0.2
0.24
0.32
N-Ch
15
VGS = -10 V, VDS = -5 V
P-Ch
-10
VDS = 15 V, ID = 3.7 A
N-Ch
6
VDS = -15 V, ID = -2.9 A
P-Ch
4
N-Channel
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
N-Ch
320
Ω
A
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
P-Channel
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
P-Ch
350
N-Ch
225
P-Ch
260
N-Ch
85
P-Ch
100
pF
pF
pF
NDS9952A.SAM
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Type
N-Channel
VDD = 10 V, ID = 1 A,
VGEN = 10 V, RGEN = 6 Ω
Min
Typ
Max
Units
N-Ch
10
15
ns
P-Ch
9
40
N-Ch
13
20
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
Turn - On Rise Time
tr
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
P-Channel
VDD = -10 V, ID = -1 A,
VGEN = -10 V, RGEN = 6 Ω
Total Gate Charge
N-Channel
VDS = 10 V,
ID = 3.7 A, VGS = 10 V
Gate-Source Charge
Qgs
Qgd
P-Channel
VDS = -10 V,
ID = -2.9 A, VGS = -10 V
Gate-Drain Charge
P-Ch
21
40
N-Ch
21
50
P-Ch
21
90
N-Ch
5
50
P-Ch
8
50
N-Ch
9.5
27
P-Ch
10
25
N-Ch
1.5
P-Ch
1.6
N-Ch
3.3
P-Ch
3.4
ns
ns
ns
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
trr
N-Ch
1.2
P-Ch
-1.2
Drain-Source Diode Forward
Voltage
VGS = 0 V, IS = 1.25 A
(Note 2)
N-Ch
0.8
1.3
VGS = 0 V, IS = -1.25 A
(Note 2)
P-Ch
-0.8
-1.3
Reverse Recovery Time
VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs
N-Ch
75
VGS = 0 V, IF = -1.25 A, dIF/dt = 100 A/µs
P-Ch
100
A
V
ns
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD (t ) =
T J−TA
R θJ A(t )
=
T J−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS (ON )
TJ
Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9952A.SAM
Typical Electrical Characteristics: N-Channel
8.0
3
6.0
R DS(on) , NORMALIZED
5.0
15
4.5
4.0
10
3.5
5
3.0
I
0
0
1
2
VDS , DRAIN-SOURCE VOLTAGE (V)
DRAIN-SOURCE ON-RESISTANCE
VGS =10V
D
, DRAIN-SOURCE CURRENT (A)
20
R DS(on) , NORMALIZED
1.2
1
0.8
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
DRAIN-SOURCE ON-RESISTANCE
R DS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V G S = 10V
6.0
8.0
10
1
0
3
6
9
I D , DRAIN CURRENT (A)
12
15
VGS = 10 V
TJ = 125°C
1.5
25°C
1
-55°C
0.5
150
0
3
6
9
I D , DRAIN CURRENT (A)
12
15
Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
1.2
V DS = 10V
TJ = -55°C
125°C
8
Vth , NORMALIZED
25°C
6
4
2
1
2
3
4
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. N-Channel Transfer
Characteristics.
5
GATE-SOURCE THRESHOLD VOLTAGE
10
I D , DRAIN CURRENT (A)
5.0
1.5
2
I D = 3.7A
Figure 3. N-Channel On-Resistance Variation with
Temperature.
0
4.5
Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
1.6
0.6
-50
4.0
2
0.5
3
Figure 1. N-Channel On-Region Characteristics.
1.4
VGS = 3.5V
2.5
V DS = V GS
I D = 250µA
1.1
1
0.9
0.8
0.7
0.6
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
NDS9952A.SAM
1.12
10
I D = 250µA
I S , REVERSE DRAIN CURRENT (A)
5
1.08
1.04
1
0.96
0.92
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
1
0.5
25°C
-55°C
0.01
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature.
0.4
0.6
0.8
1
1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature.
10
1000
I D = 3.7A
500
C iss
300
C oss
200
100
f = 1 MHz
C rss
V GS = 0V
50
0.1
0.2
0.5
1
2
5
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
Figure 9. N-Channel Capacitance Characteristics.
V GS , GATE-SOURCE VOLTAGE (V)
800
CAPACITANCE (pF)
TJ = 125°C
0.1
0.001
0.2
150
V GS = 0V
V DS = 10V
20V
8
15V
6
4
2
0
0
2
4
6
8
Q g , GATE CHARGE (nC)
10
12
Figure 10. N-Channel Gate Charge Characteristics.
T J = -55°C
V DS =10V
8
25°C
125°C
6
4
2
FS
, TRANSCONDUCTANCE (SIEMENS)
10
g
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
Typical Electrical Characteristics: N-Channel (continued)
0
0
2
4
6
I D , DRAIN CURRENT (A)
8
10
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
NDS9952A.SAM
Typical Electrical Characteristics: P-Channel (continued)
-20
3
-8.0
-7.0
R DS(on) , NORMALIZED
-6.0
-15
-5.5
-5.0
-10
-4.5
-4.0
-5
D
-3.5
I
-3.0
0
0
-1
V
DS
-2
-3
, DRAIN-SOURCE VOLTAGE (V)
-4
DRAIN-SOURCE ON-RESISTANCE
, DRAIN-SOURCE CURRENT (A)
VGS = -10V
R DS(on), NORMALIZED
1
0.8
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
DRAIN-SOURCE ON-RESISTANCE
R DS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V G S = -10V
-5.5
-6.0
1.5
-7.0
-8.0
-10
1
0
-3
-6
-9
I D , DRAIN CURRENT (A)
-12
-15
V GS = -10V
TJ = 125°C
1.5
25°C
1
-55°C
0.5
150
Figure 14. P-Channel On-Resistance Variation with
Temperature.
0
-3
-6
-9
I D , DRAIN CURRENT (A)
-12
-15
Figure 15. P-Channel On-Resistance Variation with
Drain Current and Temperature.
1.2
V DS = -10V
25°C
125°C
V th , NORMALIZED
-8
TJ = -55°C
-6
-4
-2
-1
-2
-3
-4
-5
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 16. P-Channel Transfer Characteristics.
-6
GATE-SOURCE THRESHOLD VOLTAGE
-10
ID , DRAIN CURRENT (A)
-5.0
2
I D = -2.9A
1.2
0
-4.5
Figure 13. P-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
1.6
0.6
-50
-4.0
2
0.5
-5
Figure 12. P-Channel On-Region Characteristics.
1.4
VGS = -3.5V
2.5
VDS = V GS
1.1
I D = -250µA
1
0.9
0.8
0.7
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
Figure 17. P-Channel Gate Threshold Variation
with Temperature.
NDS9952A.SAM
Typical Electrical Characteristics: P-Channel (continued)
10
I D = -250µA
5
1.08
-I S , REVERSE DRAIN CURRENT (A)
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.1
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
1
0.5
0.001
0.2
-55°C
0.4
0.6
0.8
1
1.2
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 19. P-Channel Body Diode Forward
Voltage Variation with Current and
Temperature.
10
-V GS , GATE-SOURCE VOLTAGE (V)
800
500
C iss
CAPACITANCE (pF)
25°C
0.01
1000
300
C oss
200
f = 1 MHz
C rss
V GS = 0V
50
0.1
T = 125°C
J
0.1
Figure 18. P-Channel Breakdown Voltage
Variation with Temperature.
100
V GS = 0V
0.2
0.5
1
2
5
10
-VDS , DRAIN TO SOURCE VOLTAGE (V)
30
Figure 20. P-Channel Capacitance Characteristics.
I D = -2.9A
V DS = -10V
-20V
8
-15V
6
4
2
0
0
2
4
6
8
Q g , GATE CHARGE (nC)
10
12
Figure 21. P-Channel Gate Charge Characteristics.
6
TJ = -55°C
25°C
4
125°C
3
2
1
g
FS
, TRANSCONDUCTANCE (SIEMENS)
V DS = -15V
5
0
0
-2
ID
-4
-6
, DRAIN CURRENT (A)
-8
-10
Figure 22. P-Channel Transconductance Variation
with Drain Current and Temperature.
NDS9952A.SAM
Typical Thermal Characteristics: N & P-Channel
5
I D , STEADY-STATE DRAIN CURRENT (A)
STEADY-STATE POWER DISSIPATION (W)
2.5
Total Power for Dual Operation
2
1a
Power for Single Operation
1.5
1b
1
1c
4.5"x5" FR-4 Board
TA = 25 o C
Still Air
0.5
0
0.2
0.4
0.6
0.8
2oz COPPER MOUNTING PAD AREA (in 2 )
1
3
1b
1c
2
4.5"x5" FR-4 Board
TA = 2 5 o C
Still Air
1
VG S = 1 0 V
0
0.1
0.2
0.3
0.4
2oz COPPER MOUNTING PAD AREA (in 2 )
10
0u
1m s
s
4
3
1a
1b
2
1c
4.5"x5" FR-4 Board
TA = 2 5 o C
I D , DRAIN CURRENT (A)
10
3
0.1
0.2
0.3
0.4
2oz COPPER MOUNTING PAD AREA (in 2 )
0.5
10
10
3
RD
S(O
N)
LIM
1m
IT
10
10
1
0m
10
10
s
1s
10
s
DC
VGS = 10V
0.1
SINGLE PULSE
R
0.01
0.1
0m
ms
θJ A
= See Note 1c
T A = 25°C
0.2
0.5
1
2
5
10
30
50
V DS , DRAIN-SOURCE VOLTAGE (V)
Figure 26. N-Channel Maximum Safe Operating
Area.
Figure 25. P-Ch Maximum Steady- State
Drain Current versus Copper Mounting
Pad Area.
30
S(O
IT
0.3
0.03
VG S = - 1 0 V
0
RD
LIM
N)
1
Still Air
1
0.5
30
5
I D , STEADY-STATE DRAIN CURRENT (A)
1a
Figure 24. N-Ch Maximum Steady- State
Drain Current versus Copper Mounting
Pad Area.
Figure 23. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
-I D , DRAIN CURRENT (A)
4
0u
s
s
ms
s
1s
0.3
V GS = -10V
0.1
10
s
DC
SINGLE PULSE
R
0.03
θJ A
= See Note 1c
T A = 25°C
0.01
0.1
0.2
0.5
1
2
5
10
- V DS , DRAIN-SOURCE VOLTAGE (V)
30
50
Figure 27. P-Channel Maximum Safe Operating
Area.
NDS9952A.SAM
Typical Thermal Characteristics: N & P-Channel
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0 .5
D = 0.5
0 .2
0.2
R JA (t) = r(t) * R JA
θ
θ
R JA = See Note 1c
θ
0.1
0 .1
0.05
0 .0 5
P(pk)
0.02
0 .0 2
0.01
0 .0 1
t1
Single Pulse
0 .0 0 5
t2
TJ - T
= P * R JA (t)
θ
Duty Cycle, D = t 1 / t 2
A
0 .0 0 2
0 .0 0 1
0 .0001
0 .001
0 .0 1
0 .1
1
10
100
300
t 1 , TIME (sec)
Figure 28. Transient Thermal Response Curve.
Note:
Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
ton
VDD
t d(on)
R GEN
tf
90%
90%
V OUT
D
VGS
tr
RL
V IN
to f f
t d(off)
VO U T
10%
10%
DUT
G
90%
V IN
S
50%
50%
10%
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit.
Figure 30. N or P-Channel Switching Waveforms.
NDS9952A.SAM
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST
FASTr™
GTO™
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
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Rev. E
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