NDT014

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. September 1996 NDT014 N-Channel Enhancement Mode Field Effect Transistor General Description Features Power SOT N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 2.7A, 60V. RDS(ON) = 0.2Ω @ VGS = 10V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. _________________________________________________________________________________________________________ D G Absolute Maximum Ratings Symbol Parameter VDSS D D S G S T A = 25°C unless otherwise noted NDT014 Units Drain-Source Voltage 60 V VGSS Gate-Source Voltage ±20 V ID Drain Current ±2.7 A - Continuous (Note 1a) - Pulsed PD Maximum Power Dissipation ±10 (Note 1a) 3 (Note 1b) 1.3 (Note 1c) TJ,TSTG Operating and Storage Temperature Range W 1.1 -65 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W * Order option J23Z for cropped center drain lead. © 1997 Fairchild Semiconductor Corporation NDT014 Rev. C1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V IDSS Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V 25 µA VDS = 48 V, VGS = 0 V, TJ=125°C 250 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA 3 4 V 0.2 Ω ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2 RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 1.6 A 0.18 gFS Forward Transconductance VDS = 25 V, ID = 1.6 A 2 VDS = 25 V, VGS = 0 V, f = 1.0 MHz 155 pF 60 pF 15 pF S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD =30 V, ID = 10 A, VGEN = 10 V, RGEN = 24 Ω VDS = 48 V, ID = 10 A, VGS = 10 V 10 20 ns 64 100 ns 10 20 ns 10 20 ns 5 11 nC 1.2 3.1 nC 2 5.8 nC NDT014 Rev. C1 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current 2.7 A ISM Maximum Pulsed Drain-Source Diode Forward Current 22 A VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.7A trr Reverse Recovery Time VGS = 0 V, IF = 10 A, dIF/dt = 100 A/µs 0.95 (Note 2) 1.6 V 140 ns Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD( t) = T J−TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 42oC/W when mounted on a 1 in2 pad of 2oz copper. b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper. c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDT014 Rev. C1 Typical Electrical Characteristics 8 2.5 V = 10V VGS = 5.5V 8.0 7.0 R DS(on), NORMALIZED 6 6.5 4 6.0 5.5 2 5.0 4.5 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) GS 0 0 1 V DS 2 3 , DRAIN-SOURCE VOLTAGE (V) 8.0 1.5 10 1 2 4 6 I D , DRAIN CURRENT (A) 8 10 Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 3 I D = 2.7A 1.8 V G S = 10V R DS(ON), NORMALIZED 1.6 1.4 1.2 1 0.8 0.6 0.4 -50 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED 7.0 0 2 DRAIN-SOURCE ON-RESISTANCE 6.5 0.5 4 Figure 1. On-Region Characteristics. TJ = 125°C 2 1.5 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 150 25°C 1 -55°C 0.5 0 -25 VGS = 10 V 2.5 0 2 I J D 4 6 , DRAIN-CURRENT(A) 8 10 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 1.2 10 125°C V th , NORMALIZED 8 6 4 2 0 2 4 V GS 6 8 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 10 GATE-SOURCE THRESHOLD VOLTAGE 25°C TJ = -55°C V DS = 10V I D, DRAIN CURRENT (A) 6.0 2 V DS = V GS ID = 250µA 1.1 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDT014 Rev. C1 Typical Electrical Characteristics (continued) 10 I D = 250µA 5 I S, REVERSE DRAIN CURRENT (A) , NORMALIZED DSS BV DRAIN-SOURCE BREAKDOWN VOLTAGE 1.15 1.1 1.05 1 0.95 0.9 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 V GS = 0 V 1 0.5 T J = 125°C 25°C 0.1 -55°C 0.01 0.001 0.2 150 V 300 1 1.2 VDS = 10V , GATE-SOURCE VOLTAGE (V) I D = 2.7A 200 C iss 100 C oss 50 1.4 10 0.1 0.2 40V 9 6 C rss 3 V V GS = 0 V 20V 12 GS f = 1 MHz 20 0 0.5 1 2 5 10 20 50 0 1 2 V DS , DRAIN TO SOURCE VOLTAGE (V) t on t d(on) 5 t d(off) tf 90% 90% V OUT VOUT 10% 10% DUT G 6 t off tr RL D R GEN 4 Figure 10. Gate Charge Characteristics. VDD V IN 3 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. VGS 0.8 , BODY DIODE FORWARD VOLTAGE (V) 15 400 CAPACITANCE (pF) 0.6 SD Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. Figure 7. Breakdown Voltage Variation with Temperature. 30 0.4 INVERTED 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDT014 Rev. C1 Typical Electrical Characteristics (continued) 20 T J = -55°C VDS = 1 0 V 5 ID , DRAIN CURRENT (A) 3 10 1 m 0us s 10 25°C 125°C 2 1 2 RD S( ON )L I T MI 10 10 1 0.1 0.05 m 0m 1s 10 s DC 0.5 s s VGS = 10V SINGLE PULSE RθJ A = 42 o C/W FS , TRANSCONDUCTANCE (SIEMENS) 4 g TA = 25°C 0 0 2 4 I D 6 8 10 0.01 0.1 0.2 , DRAIN CURRENT (A) Figure 13. Transconductance Variation with Drain Current and Temperature. 0.5 1 2 5 10 VDS , DRAIN-SOURCE VOLTAGE (V) 30 60 100 Figure 14. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 R JA (t) = r(t) * R JA θ θ R JA = See Note 1 c θ P(pk) 0.01 t1 0.005 (t) θJA Duty Cycle, D = t 1 / t 2 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDT014 Rev. C1 6.70 6.20 0.10 B C B 3.10 2.90 3.25 4 1.90 A 3.70 3.30 1 6.10 1.90 3 0.84 0.60 2.30 2.30 0.95 4.60 0.10 C B LAND PATTERN RECOMMENDATION SEE DETAIL A 1.80 MAX C 0.08 C 0.10 0.00 10° 5° GAGE PLANE R0.15±0.05 R0.15±0.05 10° TYP 0° 0.25 SEATING PLANE 10° 5° 0.60 MIN 1.70 DETAIL A SCALE: 2:1 0.35 0.20 7.30 6.70 NOTES: UNLESS OTHERWISE SPECIFIED A) DRAWING BASED ON JEDEC REGISTRATION TO-261C, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) LANDPATTERN NAME: SOT230P700X180-4BN F) DRAWING FILENAME: MKT-MA04AREV3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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