NDT455N

July 1996 NDT455N N-Channel Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 11.5 A, 30 V. RDS(ON) = 0.015 Ω @ VGS = 10 V RDS(ON) = 0.02 Ω @ VGS = 4.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ________________________________________________________________________________ D G Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current D D S - Continuous (Note 1a) Maximum Power Dissipation NDT455N Units 30 V 20 V ± 11.5 A ± 40 (Note 1a) 3 (Note 1b) 1.3 (Note 1c) TJ,TSTG S T A = 25°C unless otherwise noted - Pulsed PD G Operating and Storage Temperature Range W 1.1 -65 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W © 1997 Fairchild Semiconductor Corporation NDT455N Rev.F Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V TJ = 55°C 1 µA 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA 3 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 11.5 A 1 TJ = 125°C 0.7 TJ = 125°C VGS = 4.5 V, ID = 10 A ID(on) gFS On-State Drain Current Forward Transconductance VGS = 10 V , VDS = 5 V 30 VGS = 4.5 V, VDS = 5 V 15 VGS = 10 V, ID = 11.5 A 1.5 0.9 2.2 0.013 0.015 0.019 0.03 0.018 0.02 Ω A 26 S 1220 pF 715 pF 280 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 15, VGS = 0 V, f = 1.0 MHz SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 15 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω VDS = 10 V, ID = 11.5 A, VGS = 10 V 11 20 ns 16 30 ns 48 80 ns 40 70 ns 43 61 nC 4 nC 11 nC NDT455N Rev.F Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 2.5 A 1.2 V 140 ns DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.5 A (Note 2) trr Reverse Recovery Time VGS = 0 V, IF = 2.5 A dIF/dt = 100 A/µs Notes: 1. PD (t) = T J −T A R θJA(t) = T J −T A R θJC +R θCA (t) = I 2D(t) × R DS(ON)@T J 0.845 RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is defined by users. For general reference: Applications on 4.5"x5" FR-4 PCB under still air environment, typical RθJA is found to be: a. 42oC/W with 1 in2 of 2 oz copper mounting pad. b. 95oC/W with 0.066 in2 of 2 oz copper mounting pad. c. 110oC/W with 0.0123 in2 of 2 oz copper mounting pad. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDT455N Rev.F Typical Electrical Characteristics 2.5 VGS =10V 6.0 4.0 R DS(on) , NORMALIZED 5.0 3.5 24 16 3.0 8 I DRAIN-SOURCE ON-RESISTANCE 32 4.5 D , DRAIN-SOURCE CURRENT (A) 40 0 0 0.5 1 1.5 2 2.5 2 4.0 4.5 1.5 5.0 6.0 10 1 0.5 3 VGS = 3.5V 0 8 16 24 I D , DRAIN CURRENT (A) VDS , DRAIN-SOURCE VOLTAGE (V) 1.5 1.25 R DS(on) , NORMALIZED R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE V GS = 10V 1 0.75 DRAIN-SOURCE ON-RESISTANCE 2.5 I D = 11.5A VGS = 10V 2 TJ = 125°C 1.5 25°C 1 -55°C 0.5 0 -25 0 25 50 75 100 125 0 150 8 16 T , JUNCTION TEMPERATURE (°C) VGS(th) , NORMALIZED I D , DRAIN CURRENT (A) 25°C 125°C 20 10 V GS 2.4 3.2 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4 GATE-SOURCE THRESHOLD VOLTAGE T = -55°C J 1.6 40 Figure 4. On-Resistance Variation with Drain Current and Temperature. 40 30 32 D Figure 3. On-Resistance Variation with Temperature. V DS = 10V 24 I , DRAIN CURRENT (A) J 0 0.8 40 Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. Figure 1. On-Region Characteristics. 0.5 -50 32 1.4 VDS = VGS I D = 250µA 1.2 1 0.8 0.6 0.4 -50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C) J Figure 6. Gate Threshold Variation with Temperature. NDT455N Rev.F Typical Electrical Characteristics 40 1.06 1.04 1.02 1 0.98 0.96 -25 0 T J 25 50 75 100 , JUNCTION TEMPERATURE (°C) 125 150 1 T J = 125°C 0.1 -55°C 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 V SD , BODY DIODE FORWARD VOLTAGE (V) V GS , GATE-SOURCE VOLTAGE (V) 10 2000 C iss 1000 800 C oss 500 300 f = 1 MHz V GS = 0V C rss 0.2 0.5 V DS 1 2 5 10 20 30 VDS = 5.V I D = 11.5A 10V 8 15V 6 4 2 0 0 10 , DRAIN TO SOURCE VOLTAGE (V) Figure 9. Capacitance Characteristics. 20 30 40 Figure 10. Gate Charge Characteristics. t d(on) t d(off) tf 90% 90% V OUT D R GEN t off tr RL V IN VOUT 10% 10% INVERTED DUT G 50 Q g , GATE CHARGE (nC) t on V DD VGS 1.4 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 4000 100 0.1 25°C 0.01 Figure 7. Breakdown Voltage Variation with Temperature. 200 V GS = 0V 10 1.08 I S , REVERSE DRAIN CURRENT (A) , NORMALIZED DSS I D = 250µA 0.94 -50 CAPACITANCE (pF) BV DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDT455N Rev.F 3.5 40 TJ = -55°C V DS =10V STEADY-STATE POWER DISSIPATION (W) g FS, TRANSCONDUCTANCE (SIEMENS) Typical Thermal Characteristics 25°C 30 125°C 20 10 0 0 6 12 18 24 30 1a 3 2.5 2 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) I , DRAIN CURRENT (A) D Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SOT-223 Maximum Steady- State Power Dissipation versus Copper Mounting Pad Area. 60 14 30 12 I D , DRAIN CURRENT (A) I D , STEADY-STATE DRAIN CURRENT (A) 1 1a 10 8 1b 1c 4.5"x5" FR-4 Board o TA = 25 C Still Air VGS = 10V 6 0.2 0.4 0.6 0.8 R N) LIM IT 100 us 1m s 5 1 10m s 100 ms 1s 10s DC 1 0.1 0.05 VGS = 10V SINGLE PULSE RθJA =See Note1c TA = 25°C 0.01 0.1 4 0 10 (O DS 0.5 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 2 5 10 30 50 VDS , DRAIN-SOURCE VOLTAGE (V) Figure 15. Maximum Steady-State DrainCurrent versus Copper Mounting Pad Area. Figure 16. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 R JA (t) = r(t) * R JA θ θ R JA = See Note 1 c θ P(pk) 0.01 t1 0.005 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R (t) θJA Duty Cycle, D = t 1 / t 2 0.001 0.01 0.1 1 10 100 300 t 1 , TIME (sec) Figure 17. Typical Transient Thermal Impedance Curve. Remark: Thermal characterization performed under the conditions of Note 1c. Should better thermal design employs, RθJA will be lower and reach thermal equivalent sooner. NDT455N Rev.F TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.