NE5230D

NE5230, SA5230, SE5230 Low Voltage Operational Amplifier The NE5230 is a very low voltage operational amplifier that can perform with a voltage supply as low as 1.8 V or as high as 15 V. In addition, split or single supplies can be used, and the output will swing to ground when applying the latter. There is a bias adjusting pin which controls the supply current required by the device and thereby controls its power consumption. If the part is operated at ±0.9 V supply voltages, the current required is only 110 mA when the current control pin is left open. Even with this low power consumption, the device obtains a typical unity gain bandwidth of 250 kHz. When the bias adjusting pin is connected to the negative supply, the unity gain bandwidth is typically 600 kHz while the supply current is increased to 600 mA. In this mode, the part will supply full power output beyond the audio range. The NE5230 also has a unique input stage that allows the common−mode input range to go above the positive and below the negative supply voltages by 250 mV. This provides for the largest possible input voltages for low voltage applications. The part is also internally−compensated to reduce external component count. The NE5230 has a low input bias current of typically ±40 nA, and a large open−loop gain of 125 dB. These two specifications are beneficial when using the device in transducer applications. The large open−loop gain gives very accurate signal processing because of the large “excess” loop gain in a closed−loop system. The output stage is a class AB type that can swing to within 100 mV of the supply voltages for the largest dynamic range that is needed in many applications. The NE5230 is ideal for portable audio equipment and remote transducers because of its low power consumption, unity gain bandwidth, and 30 nV/√Hz noise specification. Features http://onsemi.com 8 1 SOIC−8 D SUFFIX CASE 751 8 1 PDIP−8 N SUFFIX CASE 626 PIN CONNECTIONS N, D Packages NC −IN +IN VEE 1 2 3 4 − + 8 7 6 5 NC VCC OUTPUT BIAS ADJ. (Top View) DEVICE MARKING INFORMATION See general marking information in the device marking section on page 16 of this data sheet. • • • • • • • • • • • • Works Down to 1.8 V Supply Voltages Adjustable Supply Current Low Noise Common−mode Includes Both Rails VOUT Within 100 mV of Both Rails Pb−Free Packages are Available ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. Applications Portable Precision Instruments Remote Transducer Amplifier Portable Audio Equipment Rail−to−Rail Comparators Half−wave Rectification without Diodes Remote Temperature Transducer with 4.0 to 20 mA Output Transmission © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 4 1 Publication Order Number: NE5230/D NE5230, SA5230, SE5230 MAXIMUM RATINGS Rating Single Supply Voltage Dual Supply Voltage Input Voltage (Note 1) Differential Input Voltage (Note 1) Common−Mode Voltage (Positive) Common−Mode Voltage (Negative) Power Dissipation (Note 2) Thermal Resistance, Junction−to−Ambient N Package D Package VCM VCM PD RqJA Symbol VCC VS VIN Value 18 ±9 ±9 (18) ±VS VCC + 0.5 VEE − 0.5 500 130 182 150 0 to 70 −40 to 85 −40 to 125 Indefinite Tstg Tsld −65 to 150 230 Unit V V V V V V mW °C/W Operating Junction Temperature (Note 2) Operating Temperature Range NE SA SE TJ TA °C °C 80 Output Short−Circuit Duration to Either Power Supply Pin (Notes 2 and 3) Storage Temperature Lead Soldering Temperature (10 sec max) s °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Can exceed the supply voltages when VS ≤ ±7.5 V (15 V). 2. The maximum operating junction temperature is 150°C. At elevated temperatures, devices must be derated according to the package thermal resistance and device mounting conditions. Derate above 25°C at the following rates: N package at 7.7 mW/°C D package at 5.5 mW/°C. 3. Momentary shorts to either supply are permitted in accordance to transient thermal impedance limitations determined by the package and device mounting conditions. RECOMMENDED OPERATING CONDITIONS Characteristic Single Supply Voltage Dual Supply Voltage Common−Mode Voltage (Positive) Common−Mode Voltage (Negative) Temperature NE Grade SA Grade SE Grade Value 1.8 to 15 ±0.9 to ±7.5 VCC + 0.25 VEE − 0.25 0 to +70 −40 to +85 −40 to +125 Unit V V V V °C http://onsemi.com 2 NE5230, SA5230, SE5230 DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply, RL = 10 kW, full input common−mode range, over full operating temperature range. Characteristic NE5230, SA5230 Offset Voltage Drift Offset Current VOS VOS IOS TA = 25°C TA = Tlow to Thigh Drift Bias Current IOS IB TA = 25°C TA = Tlow to Thigh Any Any Any High Low High Low High Low TA = 25°C TA = Tlow to Thigh Drift Supply Current IB IS VS = ±0.9 V TA = Tlow to Thigh TA = 25°C VS = ±7.5 V TA = Tlow to Thigh Common−Mode Input Range Common−Mode Rejection Ratio VCM CMRR VS = ±7.5 V Power Supply Rejection Ratio PSRR VOS ≤ 6 mV, TA = 25°C VOS ≤ 6 mV, TA = Tlow to Thigh RS = 10 kW; VCM = ±7.5 V; TA = 25°C RS = 10 kW; VCM = ±7.5 V; TA = Tlow to Thigh TA = 25°C VOS v 6 mV, TA = Tlow to Thigh Load Current Source Sink Source Sink Source Sink Source Sink IL VS = ±0.9 V; TA = 25°C VS = ±0.9 V; TA = 25°C VS = ±7.5 V; TA = 25°C VS = ±7.5 V; TA = 25°C VS = ±0.9 V; TA = Tlow to Thigh VS = ±0.9 V; TA = Tlow to Thigh VS = ±7.5 V; TA = Tlow to Thigh VS = ±7.5 V; TA = Tlow to Thigh High Low High Low High Low TA = 25°C Low High Low High Low High Low High Any Any Any Any High Low High Low High High High High Any Any Any Any 1.0 2.0 4.0 5.0 V− − 0.25 V− 85 80 90 85 75 80 4.0 5.0 6 7 16 32 5 6 10 15 mA 105 95 dB 95 V+ 320 1100 2.0 2.0 110 600 0.5 0.3 40 20 0.4 3.0 2.0 3.0 3.0 3.0 4.0 5.0 50 30 100 60 1.4 1.4 150 60 200 150 4.0 4.0 160 750 250 800 550 1600 600 1700 + 0.25 V+ dB V mA mA nA/°C nA nA/°C mV/°C nA mV Symbol Test Conditions Bias Min Typ Max Unit For NE5230 devices, Tlow = 0°C and Thigh = +70°C. For SA5230 devices, Tlow = −40°C and Thigh = +85°C. http://onsemi.com 3 NE5230, SA5230, SE5230 DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply, RL = 10 kW, full input common−mode range, over full operating temperature range. Characteristic SE5230 Offset Voltage VOS VOS IOS TA = 25°C TA = Tlow to Thigh Drift Bias Current IOS IB TA = 25°C TA = Tlow to Thigh Drift Offset Current Any Any Any High Low High Low High Low TA = 25°C TA = Tlow to Thigh Drift Supply Current IB IS VS = ±0.9 V TA = Tlow to Thigh TA = 25°C VS = ±7.5 V TA = Tlow to Thigh Common−Mode Input Range Common−Mode Rejection Ratio VCM CMRR VS = ±7.5 V Power Supply Rejection Ratio PSRR VOS ≤ 6 mV, TA = 25°C VOS ≤ 20 mV, TA = Tlow to Thigh RS = 10 kW; VCM = ±7.5 V; TA = 25°C RS = 10 kW; VCM = ±7.5 V; TA = Tlow to Thigh TA = 25°C TA = Tlow to Thigh Load Current Source Sink Source Sink Source Sink Source Sink IL VS = ±0.9 V; TA = 25°C VS = ±0.9 V; TA = 25°C VS = ±7.5 V; TA = 25°C VS = ±7.5 V; TA = 25°C VS = ±0.9 V; TA = Tlow to Thigh VS = ±0.9 V; TA = Tlow to Thigh VS = ±7.5 V; TA = Tlow to Thigh VS = ±7.5 V; TA = Tlow to Thigh High Low High Low High Low TA = 25°C Low High Low High Low High Low High Any Any Any Any High Low High Low High High High High Any Any Any Any 1.0 2.0 4.0 5.0 V− − 0.25 V− 85 80 90 85 75 80 4.0 5.0 6 7 16 32 5 6 10 15 mA 105 95 dB 95 320 1100 2.0 2.0 110 600 0.5 0.3 40 20 0.4 3.0 2.0 3.0 3.0 3.0 4.0 5.0 50 30 100 60 1.4 1.4 150 60 300 300 4.0 4.0 160 750 275 850 550 1600 600 1700 V+ + 0.25 V+ dB V mA mA nA/°C nA nA/°C mV/°C nA mV Symbol Test Conditions Bias Min Typ Max Unit For SE5230 devices, Tlow = −40°C and Thigh = +125°C. http://onsemi.com 4 NE5230, SA5230, SE5230 DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply, RL = 10 kW, full input common−mode range, over full operating temperature range. Characteristic NE5230, SA5230, SE5230 Large−Signal Open−Loop Gain AVOL VS = ±7.5 V RL = 10 kW; TA = 25°C TA = Tlow to Thigh Output Voltage Swing VOUT VS = ±0.9 V TA = 25°C +SW TA = 25°C −SW TA = Tlow to Thigh; +SW TA = Tlow to Thigh; −SW TA = 25°C +SW VS = ±7.5 V TA = 25°C −SW TA = Tlow to Thigh; +SW TA = Tlow to Thigh; −SW Slew Rate Inverting Unity Gain Bandwidth Phase Margin Settling Time Input Noise Total Harmonic Distortion SR BW qM tS VINN THD TA = 25°C CL = 100 pF; TA = 25°C CL = 100 pF; TA = 25°C CL = 100 pF, 0.1% RS = 0 W; f = 1.0 kHz VS = ±7.5 V AV = 1; VIN = 500 mV; f = 1.0 kHz VS = ±0.9 V AV = 1, VIN = 500 mV; f = 1.0 kHz High Low High Low Any Any Any Any Any Any Any Any High Low High Low Any High Low High Low High High 120 60 100 50 750 750 700 700 7.30 −7.32 7.25 −7.30 7.35 −7.35 7.30 −7.35 0.25 0.09 0.6 0.25 70 2.0 5.0 30 60 0.003 0.002 V/ms V/ms MHz MHz ° ms ms nV/√Hz nV/√Hz % % V 800 800 mV 2000 750 V/mV Symbol Test Conditions Bias Min Typ Max Unit For NE5230 devices, Tlow = 0°C and Thigh = +70°C. For SA5230 devices, Tlow = −40°C and Thigh = +85°C. For SE5230 devices, Tlow = −40°C and Thigh = +125°C. http://onsemi.com 5 NE5230, SA5230, SE5230 THEORY OF OPERATION voltage moves from the range where only the NPN pair was Operational amplifiers which are able to function at operating to where both of the input pairs were operating, the minimum supply voltages should have input and output effective transconductance would change by a factor of two. stage swings capable of reaching both supply voltages Frequency compensation for the ranges where one input pair within a few millivolts in order to achieve ease of quiescent was operating would, of course, not be optimal for the range biasing and to have maximum input/output signal handling where both pairs were operating. Secondly, fast changes in capability. The input stage of the NE5230 has a the common−mode voltage would abruptly saturate and common−mode voltage range that not only includes the restore the emitter current sources, causing transient entire supply voltage range, but also allows either supply to distortion. These problems were overcome by assuring that be exceeded by 250 mV without increasing the input offset only the input transistor pair which is able to function voltage by more than 6.0 mV. This is unequalled by any properly is active. The NPN pair is normally activated by the other operational amplifier today. current source IB1 through Q5 and the current mirror Q6 and In order to accomplish the feat of rail−to−rail input Q7, assuming the PNP pair is non−conducting. When the common−mode range, two emitter−coupled differential common−mode input voltage passes below the reference pairs are placed in parallel so that the common−mode voltage, VB1 − 0.8 V at the base of Q5, the emitter current is voltage of one can reach the positive supply rail and the other gradually steered toward the PNP pair, away from the NPN can reach the negative supply rail. The simplified schematic pair. The transfer of the emitter currents between the of Figure 1 shows how the complementary emitter−coupler complementary input pairs occurs in a voltage range of transistors are configured to form the basic input stage cell. about 120 mV around the reference voltage VB1. In this way Common−mode input signal voltages in the range from the sum of the emitter currents for each of the NPN and PNP 0.8 V above VEE to VCC are handled completely by the NPN transistor pairs is kept constant; this ensures that the pair, Q3 and Q4, while common−mode input signal voltages transconductance of the parallel combination will be in the range of VEE to 0.8 V above VEE are processed only constant, since the transconductance of bipolar transistors is by the PNP pair, Q1 and Q2. The intermediate range of input proportional to their emitter currents. voltages requires that both the NPN and PNP pairs are An essential requirement of this kind of input stage is to operating. The collector currents of the input transistors are minimize the changes in input offset voltage between that of summed by the current combiner circuit composed of the NPN and PNP transistor pair which occurs when the transistors Q8 through Q11 into one output current. input common−mode voltage crosses the internal reference Transistor Q8 is connected as a diode to ensure that the voltage, VB1. Careful circuit layout with a cross−coupled outputs of Q2 and Q4 are properly subtracted from those of quad for each input pair has yielded a typical input offset Q1 and Q3. voltage of less than 0.3 mV and a change in the input offset The input stage was designed to overcome two important voltage of less than 0.1 mV. problems for rail−to−rail capability. As the common−mode Input Stage VCC R10 R11 + V Vb2 Ib1 Q3 Q4 Q10 Q11 VIN− Q1 Q2 VIN+ IOUT Q5 Q8 Q9 + V Vb1 Q6 Q7 R8 R9 VEE Figure 1. Input Stage http://onsemi.com 6 NE5230, SA5230, SE5230 Output Stage Processing output voltage swings that nominally reach to less than 100 mV of either supply voltage can only be achieved by a pair of complementary common−emitter connected transistors. Normally, such a configuration causes complex feed−forward signal paths that develop by combining biasing and driving which can be found in previous low supply voltage designs. The unique output stage of the NE5230 separates the functions of driving and biasing, as shown in the simplified schematic of Figure 2 and has the advantage of a shorter signal path which leads to increasing the effective bandwidth. This output stage consists of two parts: the Darlington output transistors and the class AB control regulator. The output transistor Q3 connected with the Darlington transistors Q4 and Q5 can source up to 10 mA to an output load. The output of NPN Darlington connected transistors Q1 and Q2 together are able to sink an output current of 10 mA. Accurate and efficient class AB control is necessary to insure that none of the output transistors are ever completely cut off. This is accomplished by the differential amplifier (formed by Q8 and Q9) which controls the biasing of the output transistors. The differential amplifier compares the summed voltages across two diodes, D1 and D2, at the base of Q8 with the summed voltages across the base−emitter diodes of the output transistors Q1 and Q3. The base−emitter voltage of Q3 is converted into a current by Q6 and R6 and reconverted into a voltage across the base−emitter diode of Q7 and R7. The summed voltage across the base−emitter diodes of the output transistors Q3 and Q1 is proportional to the logarithm of the product of the push and pull currents IOP and ION, respectively. The combined voltages across diodes D1 and D2 are proportional to the logarithm of the square of the reference current IB1. When the diode characteristics and temperatures of the pairs Q1, D1 and Q3, Q2 are equal, the relation IOP × ION − IB1 × IB1 is satisfied. Separating the functions of biasing and driving prevents the driving signals from becoming delayed by the biasing circuit. The output Darlington transistors are directly accessible for in−phase driving signals on the bases of Q5 and Q2. This is very important for simple high−frequency compensation. The output transistors can be high−frequency compensated by Miller capacitors CM1A and CM1B connected from the collectors to the bases of the output Darlington transistors. A general−purpose op amp of this type must have enough open−loop gain for applications when the output is driving a low resistance load. The NE5230 accomplishes this by inserting an intermediate common−emitter stage between the input and output stages. The three stages provide a very large gain, but the op amp now has three natural dominant poles − one at the output of each common−emitter stage. Frequency compensation is implemented with a simple scheme of nested, pole−splitting Miller integrators. The Miller capacitors CM1A and CM1B are the first part of the nested structure, and provide compensation for the output and intermediate stages. A second pair of Miller integrators provide pole−splitting compensation for the pole from the input stage and the pole resulting from the compensated combination of poles from the intermediate and output stages. The result is a stable, internally−compensated op amp with a phase margin of 70°. VCC R6 Ib1 Ib2 Ib3 Q6 Q3 Q5 CM1B Q4 VOUT CM1A IOP Vb5 Vb2 Q8 D1 Ib4 D2 Q7 Ib5 Q9 R7 Q2 ION Q1 VEE Figure 2. Output Stage http://onsemi.com 7 NE5230, SA5230, SE5230 THERMAL CONSIDERATIONS When using the NE5230, the internal power dissipation capabilities of each package should be considered. ON Semiconductor does not recommend operation at die temperatures above 110°C in the SO package because of its inherently smaller package mass. Die temperatures of 150°C can be tolerated in all the other packages. With this in mind, the following equation can be used to estimate the die temperature: Tj + Tamb ) (PD qJA) (eq. 1) Where Tamb = Ambient Temperature Tj = Die Temperature PD = Power Dissipation = (ICC x VCC) qJA = Package Thermal Resistance = 270°C/W for SO−8 in PC Board Mounting See the packaging section for information regarding other methods of mounting. qJA − 100°C/W for the plastic DIP. The maximum supply voltage for the part is 15 V and the typical supply current is 1.1 mA (1.6 mA max). For operation at supply voltages other than the maximum, see the data sheet for ICC versus VCC curves. The supply current is somewhat proportional to temperature and varies no more than 100 mA between 25°C and either temperature extreme. Operation at higher junction temperatures than that recommended is possible but will result in lower Mean Time Between Failures (MTBF). This should be considered before operating beyond recommended die temperature because of the overall reliability degradation. DESIGN TECHNIQUES AND APPLICATIONS The NE5230 is a very user−friendly amplifier for an engineer to design into any type of system. The supply current adjust pin (Pin 5) can be left open or tied through a pot or fixed resistor to the most negative supply (i.e., ground for single supply or to the negative supply for split supplies). The minimum supply current is achieved by leaving this pin open. In this state it will also decrease the bandwidth and slew rate. When tied directly to the most negative supply, the device has full bandwidth, slew rate and ICC. The programming of the current−control pin depends on the trade−offs which can be made in the designer’s application. The graphs in Figures 3 and 4 will help by showing bandwidth versus ICC. As can be seen, the supply current can be varied anywhere over the range of 100 mA to 600 mA for a supply voltage of 1.8 V. An external resistor can be inserted between the current control pin and the most negative supply. The resistor can be selected between 1.0 W to 100 kW to provide any required supply current over the indicated range. In addition, a small varying voltage on the bias current control pin could be used for such exotic things as changing the gain−bandwidth for voltage controlled low pass filters or amplitude modulation. Furthermore, control over the slew rate and the rise time of the amplifier can be obtained in the same manner. This control over the slew rate also changes the settling time and overshoot in pulse response applications. The settling time to 0.1% changes from 5.0 ms at low bias to 2.0 ms at high bias. The supply current control can also be utilized for wave−shaping applications such as for pulse or triangular waveforms. The gain−bandwidth can be varied from between 250 kHz at low bias to 600 kHz at high bias current. The slew rate range is 0.08 V/ms at low bias and 0.25 V/ms at high bias. POWER SUPPLY CURRENT (mA) 800 700 600 500 400 300 200 100 100 200 300 400 500 600700 UNITY GAIN BANDWIDTH (kHz) Figure 3. Unity Gain Bandwidth vs. Power Supply Current for VCC = ±0.9 V 1.4 1.2 ICC CURRENT (mA) 1.0 0.8 0.6 0.4 0.2 0.0 0 10 101 102 RADJ (W) 103 104 105 VCC − 15V VCC − 12V VCC − 9V VCC − 6V VCC − 3V VCC − 2V VCC − 1.8V TA − 25°C Figure 4. ICC Current vs. Bias Current Adjusting Resistor for Several Supply Voltages http://onsemi.com 8 NE5230, SA5230, SE5230 The full output power bandwidth range for VCC equals 2.0 V, is above 40 kHz for the maximum bias current setting and greater than 10 kHz at the minimum bias current setting. If extremely low signal distortion (