NIF9N05CL, NIF9N05ACL
Protected Power MOSFET
2.6 A, 52 V, N−Channel, Logic Level,
Clamped MOSFET w/ ESD Protection
in a SOT−223 Package
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Benefits
• High Energy Capability for Inductive Loads
• Low Switching Noise Generation
VDSS
(Clamped)
RDS(ON) TYP
ID MAX
52 V
107 mW
2.6 A
Features
•
•
•
•
•
•
Diode Clamp Between Gate and Source
ESD Protection − HBM 5000 V
Active Over−Voltage Gate to Drain Clamp
Scalable to Lower or Higher RDS(on)
Internal Series Gate Resistance
Pb−Free Packages are Available
Drain
(Pins 2, 4)
Gate
(Pin 1)
Applications
RG
MPWR
Overvoltage
Protection
ESD Protection
• Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
Source
(Pin 3)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage Internally Clamped
VDSS
52−59
V
Gate−to−Source Voltage − Continuous
VGS
±15
V
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp = 10 ms) (Note 1)
ID
IDM
2.6
10
A
Total Power Dissipation @ TA = 25°C (Note 1)
PD
1.69
W
Operating and Storage Temperature Range
TJ, Tstg
−55 to 150
°C
Single Pulse Drain−to−Source
Avalanche Energy (VDD = 50 V, ID(pk) = 1.17
A, VGS = 10 V, L = 160 mH, RG = 25 W)
EAS
110
mJ
Thermal Resistance,
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
RqJA
RqJA
74
169
TL
260
°C/W
SOT−223
CASE 318E
STYLE 3
MARKING DIAGRAM
GATE
DRAIN
SOURCE
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2).
2. When surface mounted to a FR4 board using minimum recommended pad
size, (Cu area 0.412 in2).
1
4
2
3
AYW
xxxxx G
G
Rating
DRAIN
(Top View)
A
= Assembly Location
Y
= Year
W
= Work Week
xxxxx = F9N05 or 9N05A
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 6
1
Publication Order Number:
NIF9N05CL/D
NIF9N05CL, NIF9N05ACL
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
52
50.8
55
54
−9.3
59
59.5
V
V
mV/°C
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = 1.0 mA, TJ = 25°C)
(VGS = 0 V, ID = 1.0 mA, TJ = −40°C to 125°C)
Temperature Coefficient (Negative)
Zero Gate Voltage Drain Current
(VDS = 40 V, VGS = 0 V)
(VDS = 40 V, VGS = 0 V, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = ±8 V, VDS = 0 V)
(VGS = ±14 V, VDS = 0 V)
IGSS
10
25
±22
±10
mA
mA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 100 mA)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 3.5 V, ID = 0.6 A)
(VGS = 4.0 V, ID = 1.5 A)
(VGS = 10 V, ID = 2.6 A)
RDS(on)
Forward Transconductance (Note 3) (VDS = 15 V, ID = 2.6 A)
1.3
1.75
−4.1
2.5
190
165
107
380
200
125
gFS
3.8
Ciss
155
250
Coss
60
100
Crss
25
40
Ciss
170
Coss
70
Crss
30
V
mV/°C
mW
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
VDS = 35 V, VGS = 0 V,
f = 10 kHz
Transfer Capacitance
Input Capacitance
Output Capacitance
VDS = 25 V, VGS = 0 V,
f = 10 kHz
Transfer Capacitance
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
pF
pF
NIF9N05CL, NIF9N05ACL
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
td(on)
275
465
ns
tr
1418
2400
td(off)
780
1320
1900
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
VGS = 4.5 V, VDD = 40 V,
ID = 2.6 A, RD = 15.4 W
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
VGS = 4.5 V, VDD = 40 V,
ID = 1.0 A, RD = 40 W
Fall Time
Turn−On Delay Time
Rise Time
VGS = 10 V, VDD = 15 V,
ID = 2.6 A, RD = 5.8 W
Turn−Off Delay Time
Fall Time
Gate Charge
VGS = 4.5 V, VDS = 40 V,
ID = 2.6 A (Note 3)
Gate Charge
VGS = 4.5 V, VDS = 15 V,
ID = 1.5 A (Note 3)
tf
1120
td(on)
242
tr
1165
td(off)
906
tf
1273
td(on)
107
tr
290
td(off)
1540
tf
1000
QT
4.5
Q1
0.9
Q2
2.6
QT
3.9
Q1
1.0
Q2
1.7
VSD
0.81
0.66
trr
730
ta
200
tb
530
QRR
6.3
ns
ns
7.0
nC
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
IS = 2.6 A, VGS = 0 V (Note 3)
IS = 2.6 A, VGS = 0 V, TJ = 125°C
Reverse Recovery Time
IS = 1.5 A, VGS = 0 V,
dIs/dt = 100 A/ms (Note 3)
Reverse Recovery Stored Charge
1.5
V
ns
mC
ESD CHARACTERISTICS
Electro−Static Discharge Capability
Human Body Model (HBM)
Machine Model (MM)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
ESD
5000
500
V
NIF9N05CL, NIF9N05ACL
TYPICAL PERFORMANCE CURVES
ID, DRAIN CURRENT (AMPS)
VDS ≥ 10 V
4
3.4 V
3.2 V
2
3V
2.8 V
2.6 V
2.4 V
1
2
3
4
5
6
7
8
9
10
4
3
TJ = −55°C
2
TJ = 25°C
1
TJ = 100°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
2
3
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1
0.4
ID = 2 A
TJ = 25°C
0.3
0.2
0.1
0
2
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
6
TJ = 25°C
3.6 V
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
3.8 V
VGS = 10, 5 & 4 V
8
10
4
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
12
0.24
1.9
1.7
6
TJ = 25°C
0.2
VGS = 4 V
0.16
0.12
0.08
VGS = 10 V
1
3
2
4
5
6
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1000000
ID = 2.6 A
VGS = 12 V
IDSS, LEAKAGE (A)
ID, DRAIN CURRENT (AMPS)
6
1.5
1.3
1.1
0.9
100000
TJ = 150°C
TJ = 100°C
10000
0.7
0.5
−50
−25
0
25
50
75
100
125
1000
30
150
35
40
45
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
4
55
NIF9N05CL, NIF9N05ACL
C, CAPACITANCE (pF)
TJ = 25°C
Ciss
400 VDS = 0 V
VGS = 0 V
Crss
300
200
Ciss
100
Coss
Crss
0
10
5
VGS
0
VDS
5
10
15
20
25
30
35
5
50
QT
VDS
4
QGS
40
VGS
QGD
3
30
2
20
1
0
10
ID = 2.6 A
TJ = 25°C
0
1
2
4
3
QG, TOTAL GATE CHARGE (nC)
5
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
500
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
100000
3
IS, SOURCE CURRENT (AMPS)
VDD = 40 V
ID = 2.6 A
VGS = 10 V
10000
t, TIME (ns)
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
td(off)
tf
1000
tr
td(on)
100
10
1
10
100
VGS = 0 V
TJ = 25°C
2
1
0
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistance Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1
ORDERING INFORMATION
Device
Package
NIF9N05CLT1
SOT−223
NIF9N05CLT1G
SOT−223
(Pb−Free)
NIF9N05ACLT1G
NIF9N05CLT3
SOT−223
NIF9N05CLT3G
SOT−223
(Pb−Free)
NIF9N05ACLT3G
Shipping†
1000 / Tape & Reel
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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