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NIF9N05CLT3

NIF9N05CLT3

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    TO261-4

  • 描述:

    MOSFET N-CH 52V 2.6A SOT223

  • 数据手册
  • 价格&库存
NIF9N05CLT3 数据手册
NIF9N05CL Protected Power MOSFET 2.6 A, 52 V, N−Channel, Logic Level, Clamped MOSFET w/ ESD Protection in a SOT−223 Package http://onsemi.com Benefits • High Energy Capability for Inductive Loads • Low Switching Noise Generation Features VDSS (Clamped) 52 V RDS(ON) TYP 107 mW ID MAX 2.6 A • • • • • • Diode Clamp Between Gate and Source ESD Protection − HBM 5000 V Active Over−Voltage Gate to Drain Clamp Scalable to Lower or Higher RDS(on) Internal Series Gate Resistance Pb−Free Packages are Available Drain (Pins 2, 4) Gate (Pin 1) RG Overvoltage Protection MPWR Applications ESD Protection • Automotive and Industrial Markets: Solenoid Drivers, Lamp Drivers, Small Motor Drivers MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Internally Clamped Gate−to−Source Voltage − Continuous Drain Current − Continuous @ TA = 25°C − Single Pulse (tp = 10 ms) (Note 1) Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 V, ID(pk) = 1.17 A, VGS = 10 V, L = 160 mH, RG = 25 W) Thermal Resistance, Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds Symbol VDSS VGS ID IDM PD TJ, Tstg EAS 2.6 10 1.69 −55 to 150 110 A W °C mJ GATE AYW F9N05 G G 2 °C/W RqJA RqJA TL 74 169 260 °C DRAIN 3 SOURCE (Top View) A = Assembly Location Y = Year W = Work Week F9N05 = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) Value 52−59 ±15 Unit V V SOT−223 CASE 318E STYLE 3 Source (Pin 3) MARKING DIAGRAM 1 4 DRAIN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2). 2. When surface mounted to a FR4 board using minimum recommended pad size, (Cu area 0.412 in2). ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 May, 2006 − Rev. 5 Publication Order Number: NIF9N05CL/D NIF9N05CL MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 V, ID = 1.0 mA, TJ = 25°C) (VGS = 0 V, ID = 1.0 mA, TJ = −40°C to 125°C) Temperature Coefficient (Negative) Zero Gate Voltage Drain Current (VDS = 40 V, VGS = 0 V) (VDS = 40 V, VGS = 0 V, TJ = 125°C) Gate−Body Leakage Current (VGS = ±8 V, VDS = 0 V) (VGS = ±14 V, VDS = 0 V) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 100 mA) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 3) (VGS = 3.5 V, ID = 0.6 A) (VGS = 4.0 V, ID = 1.5 A) (VGS = 10 V, ID = 2.6 A) Forward Transconductance (Note 3) (VDS = 15 V, ID = 2.6 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance Input Capacitance Output Capacitance Transfer Capacitance 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. VDS = 25 V, VGS = 0 V, f = 10 kHz VDS = 35 V, VGS = 0 V, f = 10 kHz Ciss Coss Crss Ciss Coss Crss 155 60 25 170 70 30 250 100 40 pF pF VGS(th) 1.3 RDS(on) 190 165 107 gFS 3.8 380 200 125 Mhos 1.75 −4.1 2.5 V mV/°C mW V(BR)DSS 52 50.8 IDSS 10 25 IGSS ±22 ±10 mA 55 54 −9.3 59 59.5 V V mV/°C mA Symbol Min Typ Max Unit http://onsemi.com 2 NIF9N05CL MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge VGS = 4.5 V, VDS = 40 V, ID = 2.6 A (Note 3) Gate Charge VGS = 4.5 V, VDS = 15 V, ID = 1.5 A (Note 3) SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage Reverse Recovery Time IS = 1.5 A, VGS = 0 V, dIs/dt = 100 A/ms (Note 3) Reverse Recovery Stored Charge ESD CHARACTERISTICS Electro−Static Discharge Capability Human Body Model (HBM) Machine Model (MM) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ESD 5000 500 V IS = 2.6 A, VGS = 0 V (Note 3) IS = 2.6 A, VGS = 0 V, TJ = 125°C VSD trr ta tb QRR 0.81 0.66 730 200 530 6.3 mC 1.5 V ns VGS = 10 V, VDD = 15 V, ID = 2.6 A, RD = 5.8 W VGS = 4.5 V, VDD = 40 V, ID = 1.0 A, RD = 40 W VGS = 4.5 V, VDD = 40 V, ID = 2.6 A, RD = 15.4 W td(on) tr td(off) tf td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 QT Q1 Q2 275 1418 780 1120 242 1165 906 1273 107 290 1540 1000 4.5 0.9 2.6 3.9 1.0 1.7 nC 7.0 nC ns 465 2400 1320 1900 ns ns Symbol Min Typ Max Unit http://onsemi.com 3 NIF9N05CL TYPICAL PERFORMANCE CURVES 6 ID, DRAIN CURRENT (AMPS) VGS = 10, 5 & 4 V 3.8 V 3.6 V 4 3.4 V 3.2 V 2 3V 2.8 V 2.6 V 2.4 V 1 2 3 4 5 6 7 8 9 10 TJ = 25°C ID, DRAIN CURRENT (AMPS) 6 VDS ≥ 10 V 5 4 3 2 1 0 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 100°C 3 4 5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 6 TJ = −55°C TJ = 25°C 0 0 Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.4 ID = 2 A TJ = 25°C 0.3 0.24 Figure 2. Transfer Characteristics TJ = 25°C 0.2 VGS = 4 V 0.16 0.2 0.1 0.12 VGS = 10 V 0 2 8 10 4 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 12 0.08 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1000000 1.9 1.7 IDSS, LEAKAGE (A) 1.5 1.3 1.1 0.9 0.7 0.5 −50 −25 0 25 50 75 100 125 150 100000 ID = 2.6 A VGS = 12 V Figure 4. On−Resistance vs. Drain Current and Gate Voltage TJ = 150°C 10000 TJ = 100°C 1000 30 35 40 45 50 55 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 NIF9N05CL TYPICAL PERFORMANCE CURVES VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 500 Ciss C, CAPACITANCE (pF) 400 VDS = 0 V 300 Crss VGS = 0 V TJ = 25°C 5 QT 4 VDS QGS 3 QGD VGS 40 50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 200 Ciss Coss Crss 2 20 100 1 0 0 1 ID = 2.6 A TJ = 25°C 2 4 3 QG, TOTAL GATE CHARGE (nC) 5 10 0 0 10 5 VGS 0 VDS 5 10 15 20 25 30 35 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Gate Charge 3 IS, SOURCE CURRENT (AMPS) 100000 VDD = 40 V ID = 2.6 A VGS = 10 V td(off) 1000 tf tr 100 td(on) VGS = 0 V TJ = 25°C 2 10000 t, TIME (ns) 1 10 1 10 RG, GATE RESISTANCE (W) 100 0 0.5 0.6 0.7 0.8 0.9 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistance Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current ORDERING INFORMATION Device NIF9N05CLT1 NIF9N05CLT1G NIF9N05CLT3 NIF9N05CLT3G Package SOT−223 SOT−223 (Pb−Free) SOT−223 SOT−223 (Pb−Free) 4000 / Tape & Reel 1000 / Tape & Reel Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NIF9N05CL PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. MILLIMETERS NOM MAX 1.63 1.75 0.06 0.10 0.75 0.89 3.06 3.20 0.29 0.35 6.50 6.70 3.50 3.70 2.30 2.40 0.94 1.05 1.75 2.00 7.00 7.30 1 0° − INCHES NOM 0.064 0.002 0.030 0.121 0.012 0.256 0.138 0.091 0.037 0.069 0.276 − D b1 4 HE 1 2 3 E b e1 e q C DIM A A1 b b1 c D E e e1 L1 HE q MIN 1.50 0.02 0.60 2.90 0.24 6.30 3.30 2.20 0.85 1.50 6.70 0° MIN 0.060 0.001 0.024 0.115 0.009 0.249 0.130 0.087 0.033 0.060 0.264 0° MAX 0.068 0.004 0.035 0.126 0.014 0.263 0.145 0.094 0.041 0.078 0.287 1 0° A 0.08 (0003) A1 L1 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN SOLDERING FOOTPRINT* 3.8 0.15 2.0 0.079 2.3 0.091 2.3 0.091 6.3 0.248 2.0 0.079 1.5 0.059 mm inches SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NIF9N05CL/D
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