NIS1050MNTBG

NIS1050 Protection Interface Circuit for PMICs with Integrated OVP Control The NIS1050 is a protection IC targeted at the latest generation of PMICs from the leading mobile phone and UMPC chipset vendors. It includes a highly stable low-current LDO and a low impedance power N-Channel MOSFET. The LDO provides a low current, five volt supply to the PMIC, and the NFET is the external pass element for the OVIC circuit. These stages combine with the internal PMIC to protect the charging circuit from low-impedance overvoltage conditions that can occur from either the AC/DC or USB supply. The NIS1050 is available in the low−profile 6-lead 2x2mm WDFN6 surface mount package. Features http://onsemi.com MARKING DIAGRAMS 1 WDFN6, 2x2 CASE 506AN PM M PM = Specific Device Code M = Date Code • Lower Power Dissipation and Higher Efficiency vs. Zener Shunt • • • Regulator LDO Highly Stable across Temperature, Operates Without Bypass Capacitors Wide 3-30 V Power Supply Voltage Input Range Low−Profile (0.75mm) 6-Lead 2x2mm WDFN6 Package ORDERING INFORMATION Device NIS1050MNTBG Package WDFN6 (Pb−Free) Shipping† 3000 / Tape & Reel Typical Applications • Power Interface for New Generation PMICs from Leading Mobile Phone and UMPC Chipset Vendors †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. PMIC OVP_SNS 3,7 6,8 2 Vbus USB NIS1050 LDO 1 4 VCHG VCHG 2 Voltage Detector V_REF_2 V_REF_1 V_IN_OKAY LDO 5 OVP_CLAMP Bandgap Reference OVP_CTL other control inputs 4 Controller A) If okay, FET is closed B) If not okay, FET is opened 10k 4.7uF Vout, OUTPUT VOLTAGE (V) 3 Over−Voltage Protection 5.30 5.25 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 −40 −15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (°C) Figure 1. Typical Application Figure 2. Output Voltage Variation with Temperature © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 0 1 Publication Order Number: NIS1050/D NIS1050 1 2 3 7 8 6 5 4 Figure 3. Pin Assignment Table 1. FUNCTIONAL PIN DESCRIPTION Pin 1 2 3, 7 4 5 6, 8 Function Source Gate Vin Ground Vout Drain Description This is the source of the power FET and connects to the PMIC pin of the same name. This pin is the gate of the FET switch. Positive input voltage to the device. Negative input voltage to the device. This is used as the internal reference for the IC. This is the output of the internal LDO. It passes the input voltage through to the output and clamps that voltage if it exceeds the regulation limit. Positive input voltage to the device. MAXIMUM RATINGS Rating Input Voltage, Operating, Steady-State (OVP_sense to Gnd) Gate-to-Source Voltage Drain Current, Peak (10 ms pulse) Drain Current, Continuous (Note 1, Steady-State) TA = 25°C TA = 85°C Total Power Dissipation @ TA = 25°C (Note 1, 2) Operating Temperature Range Non-operating Temperature Range Maximum Lead Temperature for Soldering Purposes Symbol Vin VGS IDpk ID 3.7 2.7 Pmax TJ TJ TL 750 -40 to 125 -55 to 150 260 mW °C °C °C Value -0.3 to 30 ±8 20 Unit V V A A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. 2. Dual die operation (equally−heated). THERMAL RESISTANCE RATINGS Parameter SINGLE DIE OPERATION (SELF-HEATED) Junction-to-Ambient – Steady State (Note 3) Junction-to-Ambient – Steady State Min Pad (Note 4) Junction-to-Ambient – t ≤ 5 s (Note 3) DUAL DIE OPERATION (EQUALLY-HEATED) Junction-to-Ambient – Steady State (Note 3) Junction-to-Ambient – Steady State Min Pad (Note 4) Junction-to-Ambient – t ≤ 5 s (Note 3) RqJA RqJA RqJA 58 133 40 °C/W RqJA RqJA RqJA 83 177 54 °C/W Symbol Max Unit 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). http://onsemi.com 2 NIS1050 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: Vcc (OVP_sense) = 5.0 V, TJ = 25°C) Characteristics POWER FET Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 V) TJ = 85°C Gate-to-Source Leakage Current (VDS = 0 V, VGS = ±8 V) Gate Threshold Voltage (VGS = VDS, ID = 250 mA) Negative Gate Threshold Temperature Coefficent Drain-to-Source On-Resistance (Note 5) VGS = 4.5 V, ID = 2.0 A VGS = 2.5 V, ID = 2.0 A Forward Transconductance (VDS = 5 V, ID = 2.0 A) Input Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) Output Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) Reverse Transfer Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) LDO (Unless otherwise noted, TJ = 25°C, Vin = 5.0 V) Regulated Output Voltage (Vcc = 5.5 V Io = 1 mA) Response to Input Transient (Vin 0 to 30 volts,