NIS5112_07

NIS5112 Electronic Fuse The NIS5112 is an integrated switch utilizing a high side N−channel FET driven by an internal charge pump. This switch features a SENSEFETt which allows for current sensing using inexpensive chip resistors instead of expensive, low impedance current shunts. It is designed to operate in 12 V systems and includes a robust thermal protection circuit. Features http://onsemi.com MARKING DIAGRAM 8 8 1 SOIC−8 NB CASE 751 1 x = L for thermal latch off = H for thermal auto−retry A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 112x AYWWG G • • • • • • • • • • Integrated Power Device Power Device Thermally Protected No External Current Shunt Required Enable/Timer Pin Adjustable Slew Rate for Output Voltage 9 V to 18 V Input Range 30 mW Typical Internal Charge Pump ESD Ratings: Human Body Model (HBM); 4000 V These are Pb−Free Devices Typical Applications • Hard Drives ORDERING INFORMATION Device NIS5112D1R2G Package SOIC−8 Latch Off (Pb−Free) SOIC−8 Auto−Retry (Pb−Free) Shipping † 2500 Tape & Reel 2500 / Tape & Reel NIS5112D2R2G 8 VCC †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Voltage Regulator Charge Pump Current Limit Overvoltage Clamp Thermal Latch Voltage Slew Rate Source 5, 6, 7 Current Limit 4 Enable/ Timer Enable/Timer 3 GND 1 dV/dt 2 Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2007 1 March, 2007 − Rev. 5 Publication Order Number: NIS5112/D NIS5112 Table 1. FUNCTIONAL PIN DESCRIPTION Pin 3 1 4 5,6,7 2 8 Function Enable/Timer Ground ILimit Source dV/dt VCC Description A high level signal on this pin allows the device to begin operation. Connection of a capacitor will delay turn on for timing purposes. A low input signal inhibits the operation. Negative input voltage to the device. This is used as the internal reference for the IC. A resistor between this pin and the source pin sets the current limit level. Source of power FET, which is also the switching node for the load. A capacitor from this pin to ground programs the slew rate of the output at turn on. This capacitor is discharged by an internal discharge circuit when the device is disabled via the enable pin. Positive input voltage to the device. Table 2. MAXIMUM RATINGS (Maximum ratings are those, that, if exceeded, may cause damage to the device. Electrical characteristics are not guaranteed over this range) Rating Input Voltage, Operating, Drain Voltage, Operating, Drain Current, Peak (Internally Clamped) Drain Current, Continuous (TA=25°C), (Note 2) Thermal Resistance, Junction−to−Air 0.5 in2 Copper 1.0 in2 Copper Thermal Resistance, Junction−to−Lead (Pin 8) Power Dissipation (TA = 25°C) (Note 1) Operating Temperature Range (Note 2) Nonoperating Temperature Range Lead Temperature, Soldering (10 Sec) Steady−State (Input+ to Input−) Transient (Conditions 1 ms) Steady−State (Drain to Input−) Transient (Conditions 1 ms) Symbol Vin VDD IDpk IDavg QJA 120 110 QJL Pmax TJ TJ TL 27 1.0 −40 to 175 −55 to 175 260 Value −0.3 to 18 −0.3 to 25 −0.3 to 18 −0.3 to 25 25 5.3 Unit V V A A °C/W °C/W °C/W W °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Mounted on FR−4 board, 1 in sq pad, 1 oz coverage. 2. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as specified. http://onsemi.com 2 NIS5112 Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, RLIMIT = 56 W TJ = 25°C) Characteristics POWER FET Delay Time (Enabling of Chip to Beginning of Conduction (10% of IPK)) Charging Time (Beginning of Conduction to 90% of Vout) CdV/dt = 1 mF, Cload = 1000 mF ON Resistance (ID = 2 A, TJ = −20°C) (Note 3) (ID = 2 A, TJ = 25°C) (ID = 2 A, TJ = 100°C) (Note 3) Off State Output Voltage (Vin = 12 Vdc, Enable Low, Vdc, TJ = −20°C) (Note 3) (Vin = 12 Vdc, Enable Low, TJ = 25°C) (Vin = 12 Vdc, Enable Low, TJ = 100°C) (Note 3) Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 10 kHz) THERMAL LATCH Shutdown Temperature (Note 3) Thermal Hysteresis (Auto Retry Only) (Note 3) ENABLE/TIMER Enable Voltage (Turn−on) (Rload = 2 K, TJ = −20°C) (Note 3) (Rload = 2 K, TJ = 25°C) (Rload = 2 K, TJ = 100°C) (Note 3) Enable Voltage (Turn−off) (Rload = 2 K, TJ = −20°C) (Note 3) (Rload = 2 K, TJ = 25°C) (Rload = 2 K, TJ = 100°C) (Note 3) Charging Current (Current Sourced into Timing Cap) (TJ = −20°C) (Note 3) (TJ = 25°C) (TJ = 100°C) (Note 3) OVERVOLTAGE CLAMP Output Clamping Voltage (VCC = 18 V, TJ = −20°C) (Note 3) (VCC = 18 V, TJ = 25°C) (VCC = 18 V, TJ = 100°C) (Note 3) CURRENT LIMIT Short Circuit Current Limit, (RextILimit = 56 W, TJ = −20°C) (Note 3) (RextILimit = 56 W, TJ = 25°C) (RextILimit = 56 W, TJ = 100°C) (Note 3) Overload Current Limit, (Note 3) (RextILimit = 56 W, TJ = −20°C) (RextILimit = 56 W, TJ = 25°C) (RextILimit = 56 W, TJ = 100°C) dV/dt CIRCUIT Slew Rate (CdV/dt = 1 mf) Charging Current (Current Sourced into dV/dt Cap) (TJ = −20°C) (Note 3) (TJ = 25°C) (TJ = 100°C) (Note 3) Max Capacitor Voltage TOTAL DEVICE Bias Current (Device Operational, Load Open, Vin = 12 V) Minimum Operating Voltage 3. Verified by design. IBias Vmin − − 1.45 − 2.0 9.0 mA V dV/dt 0.130 IdV/dt 67 70 71 Vmax − 80 83 84 − 90 92 96 VCC V 0.15 0.170 mA V/ms ILim−SS 2.05 2.0 1.7 ILim−OL 3.7 3.5 3.4 4.6 4.4 4.3 5.5 5.3 5.2 2.7 2.5 2.3 3.2 3.0 2.7 A A VClamp 14 14 13 15.5 15 14.5 17 16.2 16 V VENon 2.45 2.5 2.7 VENoff − − − ICharge 67 70 71 80 83 84 90 92 96 − − − 1.8 1.9 2.0 mA − − − − − − V V TSD Thyst 125 − 135 40 145 − °C °C Tdly tchg RDSon − − − 23.5 28 37 Voff − − − − − − − 396 120 120 200 − pF 27.5 32 43.5 mV 5.0 64 − − ms ms mW Symbol Min Typ Max Unit http://onsemi.com 3 NIS5112 100 10 ILimit (A) ILIMIT_OL 1 ILIMIT_SS 0 10 100 RextILimit (W) 1000 Figure 2. Current Limit Adjustment +12 V Source 56 W Current Limit NIS5112 Enable signal is compatible with open collector devices as well as most families. Enable/ Timer GND dV/dt 1 mF Load Enable GND (Typical operating conditions: Vin = 12 V, RILimit = 56 W, CdV/dt = 1 mF) Figure 3. Typical Application Circuit http://onsemi.com 4 NIS5112 Input Voltage Output Voltage Slew Rate = 0.14 V/ms Load Current Figure 4. Turn−on Waveforms for a Resistive Load of 10 W (CdV/dt = 1 mf) Input Voltage Output Voltage Slew Rate = 0.14 V/ms Load Current (i = C dV/dt) Figure 5. Turn−on Waveforms for a Load Capacitance of 3,300 mf (CdV/dt = 1 mf) http://onsemi.com 5 NIS5112 Input Voltage Vout Regulated at 15 V Load Current Figure 6. Turn−on Waveforms for an Overvoltage Condition (10 W Resistive Load) http://onsemi.com 6 NIS5112 DEVICE OPERATION Basic Operation This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output current, die temperature, turn−on di/dt and turn−on dV/dt, as well as an enable/timer function. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The dV/dt of the output voltage can be programmed by the addition of a capacitor to the dV/dt pin, or if left open, the output current will be limited by the internally controlled di/dt. The device will remain on as long as the temperature does not exceed the 135°C limit that is programmed into the chip. The current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current as long as it remains at the set level. The input overvoltage clamp also does not shut down the part, but will limit the output voltage to 15 V in the event that the input exceeds that level. The device can be turned on and off by the enable/timer function, which can also be used to reset the device after a thermal fault if the thermal latch version is chosen. An internal charge pump provides bias for the gate voltage of the internal N−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. dV/dt Source 80 mA R + − Enable R dV/dt Figure 7. dV/dt Circuit Overvoltage Clamp This circuit is comprised of an operational amplifier and current source as shown in Figure 7. The enable circuit controls a FET that keeps the slew−rate capacitor discharged any time the device is disabled. When the enable pin is released (low−to−high transition) or when power is applied with the enable pin in a high state, the dV/dt capacitor begins to charge due to the 80 mA in the current source. The amplifier controls the output voltage and tracks the voltage on the dV/dt cap scaled by a factor of 2. The output voltage will continue to ramp higher until it reaches the input voltage, or until the 15 V clamp limits it. The equation for the output slew rate is dV/dt = (I/CdV/dt) x 2. Where: I – is 80 mA (internal current source) CdV/dt – is the desired dV/dt capacitor value. The dV/dt ramp begins with a small step of about 200 mV. This step causes a current surge into the output load capacitance which can be seen in Figure 5. The peak level of this surge will be limited to the overload level of the current limit. The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the output voltage exceeds 15 V, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. Enable/Timer The enable/timer pin can function either as a direct enable pin, or as a time delay. In the enable mode, an open collector device is connected to this pin. When the device is in its low impedance mode, this pin is low and the operation of the chip is disabled. If a time delay is required, a capacitor is added to this pin. If a capacitor is added without an open collector device, the turn on will be delayed from the time at which the UVLO voltage is reached. If an open collector device is also used, the delay will start from the time that it goes into its high impedance state. The capacitor is charged by an internal current source of 80 mA (typical). The nominal trip voltage of the comparator is 2.5 V and was designed to be compatible with most logic families. In general, logic gates can be tied directly to this pin, but it is recommended that this be tested. http://onsemi.com 7 NIS5112 There is an inherent delay in the turn on of the electronic fuse, due to the method of gate drive used. The gate of the power FET is charged through a high impedance resistor, and from the time that the gate starts charging until the time that it reaches its threshold voltage, there will be no conduction. Once the gate reaches its threshold voltage, the output current will begin a controlled ramp up phase. This delay will be added to any timing delay due to the enable/timer circuit. Figure 8 shows a simplified diagram of the enable/timer circuit. Thermal Protection Circuit The temperature limit circuit senses the temperature of the Power FET and removes the gate drive if the maximum level is exceeded. The NIS5112 device has two different thermal limit versions, auto−retry and latch off. Auto−Retry Version The device will shut down when the thermal limit threshold is reached (TJ = 135°C, typical) and will not turn back on until the die temperature reduces down to 95°C (40°C hysteresis, typical). It will keep auto−retrying until the fault condition is removed or power is turned−off. Latch−Off Version Enable/ Timer 80 mA + − Enabled For the latch−off version, the device will shut down when the thermal limit threshold is reached (TJ = 135°C, typical) and will remain off until power is reset. 2.5 V Figure 8. Simplified Schematic Diagram of the Enable/Timer Circuit http://onsemi.com 8 NIS5112 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein (NIS5112), may be covered by one or more of the following U.S. patents: 6,781,502; 7,099,135. Other patents may be pending. SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). 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