NIS6150MT2TXG

+5 Volt Electronic eFuse NIS6150, NIV6150 The NIS6150 is a cost effective, resettable fuse which can greatly enhance the reliability of a USB application from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits and to protect the input side circuitry from reverse currents. It includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue its operation. www.onsemi.com Features • • • • • • • • • • • 200 mW Max RDS(on) Integrated Reverse Current Protection Adjustable Output Current Limit Protection with Thermal Shutdown IEC61000−4−2 Level 4 ESD Protection for Vbus up to ±7 kV Fast Response Overvoltage Clamp Circuit with Selectable Level Internal Undervoltage Lockout Circuit Digital Enable with Separate FLAG for Fault Identification Integrated Current Monitoring Both Latching and Auto−Retry Options Available NIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant WDFNW10, 3 x 3 CASE 515AB MARKING DIAGRAM XXXXX XXXXX ALYWG G A L Y W G (Note: Microdot may be in either location) PIN CONNECTIONS Typical Applications • • • • = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Automotive Infotainment USB 2.0/3.0/3.1 VBUS Solid State Drives Mother Boards VCC 1 SRC VCC GND SRC N/C IMON Ilim EN Vc_SEL FLAG (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2018 August, 2020 − Rev. 3 1 Publication Order Number: NIS6150/D NIS6150, NIV6150 +3.3V System Power NIV1161/NIV2161 D− D− Vcc USB Transceiver IC D+ D+ USB 2.0 Connector GND Vbus CL 22μF 4.7μF GND Vcc Source Vcc Source CIN +5V System Power Rlim 1 μF GND RMON 1kΩ NIS6150 Imon Enable EN Vc_SEL Floating or Grounded Ilim FLAG FLAG Figure 1. Typical USB 2.0 Application Circuit VCC EN EN FLAG Reverse Current FLAG Thermal Shutdown Charge Pump Source UVLO Vc_SEL Voltage Clamp Current Limit Current Sense Ilim Imon GND Figure 2. Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1, 2 VCC Positive input voltage to the device. (Low ESR capacitor of minimum 4.7 mF from VCC to GND is required) 3 GND Negative input voltage to the device. This is used as the internal reference for the IC. 4 IMON This pin can be used to monitor the output current by using an external pull−down resistor and de−coupling capacitor. 5 Vc_SEL 6 FLAG 7 EN When this pin is pulled low the eFuse is turned off. It can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device, as it has an internal pull−up. 8 Ilim A resistor between this pin and the source pin sets the overload and short circuit current limit levels. 9, 10 Source 11 N/C (EP) The Vc_SEL pin allows the overvoltage clamp to be set at either a 5.7 V or 6.5 V minimum. If a thermal fault occurs, the voltage on this pin will go to a low state to signal a monitoring circuit that the device is in thermal shutdown. Source of the internal power FET and the output terminal of the fuse (Exposed Pad) This pad to be used as heatsink only with no electrical connection. It should be connected to a large area of copper on the PCB, or to the PCB’s GND plane. www.onsemi.com 2 NIS6150, NIV6150 MAXIMUM RATINGS Rating Symbol Value Input Voltage, operating, steady−state (VCC to GND) Transient (100 ms) VCC −0.3 to +10 Output Voltage, operating, steady−state (SRC to GND) VOUT −0.3 to +20 V Voltage range on ILIM pin −0.3 to +10 Unit V VILIM −0.3 to +20 V Voltage range on Enable pin VEN −0.3 to 5 V Voltage range on FLAG pin VFLAG −0.3 to 6 V −0.3 to 5 V Voltage range on all other pins Electrostatic Discharge Human Body Model (All pins) Charged Device Model (All pins) IEC61000−4−2 Contact (Source pins, with 22 mF Csource condition) ESD ±2 ±1 ±7 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RATINGS Rating Symbol Value Unit Thermal Resistance, Junction−to−Air (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) qJA 95 °C/W Thermal Characterization Parameter, Junction−to−Lead (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) yJ−L 21 °C/W Thermal Characterization Parameter, Junction−to−Board (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) yJ−B 13 °C/W Thermal Characterization Parameter, Junction−to−Top (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) yJ−T 20 °C/W Total Continuous Power Dissipation @ TA = 25°C (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) Derate above 25°C Pmax 1.3 W 10.4 mW/°C Operating Ambient Temperature Range TA −40 to 125 °C Operating Junction Temperature Range TJ −40 to 150 °C TSTG −55 to 155 °C TL 260 °C Non−operating Temperature Range Lead Temperature, Soldering (10 Sec) www.onsemi.com 3 NIS6150, NIV6150 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 5 V, CL = 22 mF, Rlimit = 5.6 W, TA = −40 to 125°C) Symbol Characteristics Min Typ Max Unit POWER FET Delay Time (enabling of chip to ID = 100 mA with 5 W resistive load) ON Resistance (Note 1) Tdly 1500 RDS(on) 135 ms 200 mW Id 1.0 A IOFF_LEAK 1 mA TJ = 140°C (Note 2) 200 Continuous Current @ TA = 25°C (Note 2) Off State Leakage (Vin = 5 V, EN = 0) THERMAL LATCH TSD 150 175 200 °C VOUT Maximum (VCC = 10 V with Vc_SEL pin floating) Vout−clamp 6.5 6.9 7.5 V VOUT Maximum (VCC = 10 V with Vc_SEL pin pulled low (0V)) Vout−clamp 5.7 6.1 6.5 V Over Voltage Response Time Tvout−clamp 11 20 ms 3.8 4.3 V Shutdown Temperature (Note 3) UNDER/OVERVOLTAGE PROTECTION Undervoltage Lockout (Turn on, Voltage Going High) VUVLO 3.5 UVLO Hysteresis VHyst 0.35 Under Voltage Response Time, VCC Falling, −5 V/ms Tuvlo 2 6 ms 5 10 ms Under Voltage Response, VCC Rising, +5 V/ms V CURRENT LIMIT Current Limit IOL Short Circuit Current Isc Current Limit Response Time 1.2 0.15 Tilim A 0.25 0.35 A 2 10 ms REVERSE CURRENT LIMIT Reverse Current Blocking Threshold (Vout−Vin) (Note 4) Reverse Current Limit Response Time (dVin/dt = −5 V/1 ms, 20 mF Load) Vrev−th 25 100 250 mV Vrev−resp 4 7 12 ms 1 3 ms SLEW RATE CONTROL SR Slew Rate CURRENT MONITOR No Load Current (EN = high, Iload = 0 A) Gain (I − IMON/Iout, @ Iout = 1 A, RMON = 1 kW, CMON = 1 mF) Clamp Voltage of Current Monitor Imon−o 0 10 50 mA Imon−gain 2.88 3.2 3.52 mA/A VIMON_CLAMP 4.0 V ENABLE Logic Level Low (Output Disabled) Vin−low Logic Level High (Output Enabled) (Note 5) Vin−high High State Maximum Voltage Vin−max Logic Low Sink Current (VEN = 0 V) 0.4 1.1 Iin−low De−glitch Filter−delay Filter−delay 2 V V 5 V 15 35 mA 10 50 ms 0.7 V 5.0 V FLAG Fault Output Low Voltage (Fault Detected) Fault−low Fault Output High Voltage (No Fault Detected) Fault−high Logic High Source Current Flag−IOH Maximum Fan Out for Fault Signal Fan www.onsemi.com 4 2.5 60 mA 2 Units NIS6150, NIV6150 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 5 V, CL = 22 mF, Rlimit = 5.6 W, TA = −40 to 125°C) Characteristics Symbol Min Typ Max 300 100 100 800 200 200 Unit TOTAL DEVICE IBias Bias Current Operational (ILoad = 0 A, EN = 1, FLAG = high) Shutdown (EN = 0) Thermal Fault mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Pulse test: Pulse width 300 s, duty cycle 2% 2. Verified by design. 3. eFuse is latched off until the En/Fault pin is pulled low and then released or a power on reset is applied to the device. If an auto−retry part is used the device will automatically attempt to turn on once the internal temperature is less than 135°C. 4. Once the device has entered shutdown mode due to a reverse current event, it will re-enable its output when VIN > VOUT for at least 100 ms. The slew rate SR will be applied when the output is re-enabled. 5. A voltage level higher than Vin−high min (1.1 V) must be present to ensure a Logic Level High on the Enable pin. 4.0 IOL & ISC CURRENT (A) 3.5 3.0 2.5 2.0 1.5 IOL 1.0 0.5 0 ISC 1 3 5 9 7 11 13 Rlimit (W) Figure 3. Current Limit vs. Rlimit − Calculated www.onsemi.com 5 15 NIS6150, NIV6150 APPLICATIONS INFORMATION Basic Operation the VBUS voltage is adjusted for cable loss compensation. This operation can be seen in Figure 5. This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The output voltage, which is controlled by an internal dv/dt circuit, will slew from 0 V to the rated output voltage in 1 ms. The device will remain on as long as the temperature does not exceed the 175°C limit that is programmed into the chip. The internal current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage in the event that the input exceeds the Vclamp level. This operation can be seen in Figure 5. An internal charge pump provides bias for the gate voltage of the internal n−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. The VCC line can generate spike noise in fast transient conditions such as short circuit, and this high peak can cause over−stress and malfunction. To prevent this, a low ESR capacitor (i.e. MLCC) of at least 4.7 mF is required. Thermal Protection The NIS6150 includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175°C, the device will shut down, and remove power from the load. If a latching device is used, output power can be restored by either recycling the input power or toggling the enable pin. An auto−retry device will automatically try to restore output power on its own. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. FLAG The FLAG pin sends information to other devices regarding the state of the chip. This pin is connected to an internal pull−up so that it behaves as active high. The FLAG pin remains at logic level high during normal operation and gets pulled low and subsequently turns the device off when one of the following conditions occurs: 1. EN pin set to Logic Level Low (Output Disabled) 2. Thermal fault 3. UVLO − Undervoltage Lockout 4. Reverse current fault Enable The Enable feature provides a digital interface to control the output of the eFuse. This pin is meant for push−pull operation and is connected to an internal pull−up so that it behaves as active high. When pulled low by an external circuitry (below 0.5 V), the eFuse output is turned off. Leakage current in this condition is described in the electrical characteristics table. Reverse Current Protection The NIS6150 monitors and protects against reverse current events, which can be the result of a malfunction in the power supply or noise induced in the input voltage rail under certain load characteristics (for example, when the load is largely capacitive). The protection mechanism disables the eFuse’s output and triggers when the reverse voltage drop exceeds 100 mV in magnitude and this condition remains for at least 4 ms. The NIS6150 automatically re−enables its output once the input voltage exceeds the output voltage for at least 100 ms. IMON (Current Monitor) The current monitor ”IMON” pin provides a small current proportional to the main device current which is passing through the device. This pin must have a decoupling capacitor to filter out internal sampling noise. A resistor connected between the IMON pin and GND converts the IMON current into a GND referenced voltage. The recommended resistor value of 1 kW will give about 1 V for every 1 A of device current. The IMON voltage to output current relationship is given in the below equation. Overvoltage Clamp The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds the Vclamp voltage, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. The Vc_SEL pin can be used to select the Vclamp level. By allowing this pin to float high, the Vclamp value will be set to 6.5 − 7.5 V. By pulling this pin low (to 0V), the Vclamp value will be set to 5.7 − 6.5 V. This allows the NIS6150 to be used in both short and long haul USB applications where V MON + 3.2 R MON I ǒ1000 Ǔ d Appropriate RMON value should be selected keeping the max rating of the device of the interfacing circuit in mind. The value should be limited to 3 kW for best operation of the IMON function. This pin can be floated if this function is not needed thus saving a few mA of leakage current. www.onsemi.com 6 NIS6150, NIV6150 Latching vs. Auto−Retry device is allowed to pull−up the output to its normal, high state. Instead of remaining in thermal shutdown, an Auto−retry device (MT2) will automatically attempt to pull up the output once the die temperature cools to < 135°C. If the fault remains on the output during this attempt, the device will once again enter a short period of current limiting that will eventually lead to thermal shutdown for which the auto−retry process will repeat indefinitely. This device features two options regarding its reset ability after a thermal shutdown event. These are called latching and auto−retry which are respectively marked MT1 and MT2 as part number suffixes. Upon reaching a thermal shutdown state, a latching device (MT1) will remain shutdown with no power supplied to the output (SRC pins). The only way to reset the device is to either perform a power cycle on the VCC bus or pull the EN pin low (