NIS6452MT2TWG

Electronic Fuse, +3.3/+5 Volt NIS6432, NIS6452 The NIS64x2 is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits and to protect the input side circuitry from reverse currents. It includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue its operation. www.onsemi.com Features WQFN12 CASE 510BM MARKING DIAGRAM XXXXX ALYWG G XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Typical Applications PIN CONNECTIONS • Hard Drives • Solid State Drives • Mother Boards 12 1 VIN 2 VIN 3 VIN GND • 42 mW Typical Digital and Tristate Enable Integrated Reverse Current Protection Thermally Protected Integrated Soft−Start Circuit Fast Response Overvoltage Clamp Circuit Internal Undervoltage Lockout Circuit Internal Charge Pump Load Current Monitor Pin ESD Ratings: Human Body Model (HBM); 2000 V Charged Device Model (CDM); 2000 V Latch−Up; Class 1 These Devices are Pb−Free and are RoHS Compliant VOUT 11 NIS6432 NIS6452 VOUT 10 GND • • • • • • • • • • VOUT 9 ILIM 8 dV/dt 7 13 5 En/Fault ISENSE 4 SASIN 6 ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2017 November, 2020 − Rev. 5 1 Publication Order Number: NIS6432/D NIS6432, NIS6452 3.3V/5V Source VIN VOUT LOAD NIS64x2 SASIN ISENSE ILIM EN/Fault SAS Disable Fault RLIM GND dV/dt EN RSENSE 1mF 1kW Cdvdt Figure 1. Typical Application Circuit 3.3V/5V Source VIN VOUT LOAD NIS64x2 SASIN ISENSE ILIM EN/Fault SAS Disable Fault RLIM GND dV/dt EN RSENSE 1kW Cdvdt +12 Source 11 Source Source Source Source Source Vcc 3 Enable/ Fault 10 9 8 7 6 ILIMIT 4 RLIM NIS5x2x dV/dt 2 LOAD GND 1 Figure 2. Common Thermal Shutdown with another eFuse www.onsemi.com 2 1mF NIS6432, NIS6452 VIN EN/Fault Enable/Fault SASIN SAS Disable ISENSE Current Monitor Charge Pump Current Limit VOUT Thermal Shutdown UVLO ILimit dV/dt Control dV/dt Voltage Clamp Figure 3. Block Diagram www.onsemi.com 3 GND NIS6432, NIS6452 Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1,2,3 VIN 4 SASIN Positive input voltage to the device. 5 EN/Fault 6 ISENSE Current Sense Pin. Connect a 1 kW 1% resistor and a 1 mF capacitor to ground. 7 dV/dt The internal dV/dt circuit controls the slew rate of the output voltage at turn on. 8 ILIM 9,10,11 VOUT Source of the internal power FET and the output terminal of the fuse 12,13 GND Negative input voltage to the device. This is used as the internal reference for the IC. When this pin is pulled high the eFuse is turned off. This pin is a tri−state, bidirectional interface. It can be pulled to ground with an external open−drain or open collector device to shut down the eFuse. It can also be used as a status indicator; if the voltage level is intermediate (around 1.4 V), the eFuse is in thermal shutdown. If the voltage level is high (around 3 V) the eFuse is operating normally. Do not actively drive this pin to any voltage. Do not connect a capacitor to this pin. A resistor between this pin and ground pin sets the overload and short circuit current limit levels. Table 2. MAXIMUM RATINGS Rating Input Voltage, operating, steady−state (VIN to GND) Transient (100 ms) Symbol Value Unit VIN −0.3 to +14 V −0.3 to +15 Voltage range on EN/Fault pin −0.3 to 6 Voltage range on SASIN pin −0.3 to 6 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. THERMAL RATINGS Thermal Resistance, Junction to Air (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) qJA 75 °C/W Thermal Resistance, Junction−to−Lead (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−L 12 °C/W Thermal Resistance, Junction−to−Board (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−B 12 °C/W Thermal Resistance, Junction−to−Case Top (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−T 5 °C/W Total Power Dissipation @ TA = 25°C (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) Derate above 25°C Pmax 1.67 W 13.4 mW/°C Operating Ambient Temperature Range TA −40 to 125 °C Operating Junction Temperature Range TJ −40 to 150 °C TSTG −55 to 155 °C TL 260 °C Non−operating Storage Temperature Range Lead Temperature, Soldering (10 Sec) www.onsemi.com 4 NIS6432, NIS6452 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VIN = 5 V, dV/dt pin open, RLIM = 10 kW, TA = 25°C) Symbol Characteristics Min Typ Max Unit 42 60 mW POWER FET RDS(on) ON Resistance (Note 4) TJ = 140°C (Note 5) 62 Continuous Current (Ta = 25°C, 0.5 sq in pad) (Note 4) (Ta = 80°C, minimum copper) Id A 5 3.8 Off State Leakage (Vin = 5 V, EN = 0 V) Ileak 1 mA THERMAL LATCH Shutdown Temperature (Note 1) TSD 150 175 200 °C Vout−clamp 3.6 6.3 3.9 6.5 4.4 7.0 V Undervoltage Lockout (Turn on, Voltage Going High) VUVLO 2.3 2.8 V UVLO Hysteresis VHyst UNDER/OVERVOLTAGE PROTECTION VOUT Maximum (VCC = 10 V) NIS6432 NIS6452 0.4 V CURRENT LIMIT Overload Current Limit (overload/trigger), RLIM = 10 kW IOL Short Circuit Current Limit, RLIM = 10 kW ISC 2.34 4.3 Current Limit Response Time Tilim 5.5 2.7 A 3.06 A 40 ms LOAD CURRENT MONITORING ISENSE Load Monitor Sense Current, RSENSE = 1 kW 1 mA/A REVERSE CURRENT LIMIT Reverse Current Limit (Note 5) IREVERSE Reverse Current Limit Response Time (dVin/dt = −5 V/1 ms, 20 mF Load) TIREVERSE 1.2 5 1.78 A 10 ms SLEW RATE CONTROL Slew Rate (No dV/dt capacitor) SR 1.0 ms ENABLE/FAULT Output Logic Level Low (Output Disabled) EN(VOL) Output Logic Level Mid (Thermal Fault, Output Disabled) EN(MID) 0.9 Output Logic Level High (Output Enabled) EN(VOH) 2.1 Logic Low Sink Current (Venable = 0 V) EN(ISink) Logic High Leakage Current for External Switch (Venable = 3.3 V) Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) 0.8 V 1.4 1.95 V 12 20.24 mA EN(ILeak) 1 mA EN(Fanout) 3 Units V SAS DISABLE Logic Level Low (Output Enabled) SASIN(VIL) Logic Level High (Output Disabled) SASIN(VIH) De−glitch Filter Delay SASTdly 0.3 V 2 1.2 V 50 ms TOTAL DEVICE IBias Bias Current Operational (ILoad = 0 A) mA 300 Shutdown (EN = 0), (Note 2) 160 Fault 100 www.onsemi.com 5 120 NIS6432, NIS6452 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VIN = 5 V, dV/dt pin open, RLIM = 10 kW, TA = 25°C) Characteristics Symbol Min Typ Max EN/Fault Level VOUT State Latch UVLO EN(VOL) off no TSD EN(MID) off yes, (Note 1) EN(MID) off no, (Note 5) EN(VOH) on N/A Unit FAULT EVENTS Under Voltage Lock Out Thermal Shutdown Reverse Current Protection Ireverse No Fault (Vin > UVLO) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. eFuse is latched off until the En/Fault pin is pulled low and then released, the SAS Disable pin is pulled high and then released or a power on reset is applied to the device. 2. Does not include fan out of Enable/Fault function. 3. Pulse test: Pulse width 300 s, duty cycle 2% 4. Verified by design. 5. Once the device has entered shutdown mode due to a reverse current event, it will re−enable its output when VIN > VOUT for at least 100 ms. The slew rate SR will be applied when the output is re−enabled. www.onsemi.com 6 NIS6432, NIS6452 100 35 30 25 TIME (ms) OUTPUT VOLTAGE RAMP TIME, VOUT FROM 10 TO 90% OF VCC (ms) TYPICAL CHARACTERISTICS 20 15 85°C 25°C 10 5 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1 0 5 Figure 5. Thermal Trip Time vs Power Dissipation 3 UVLO Rising UVLO Falling VCLAMP (V) VOLTAGE (V) 2.5 1.5 1 0.5 0 −40 UVLO Hysteresis −20 0 20 40 60 80 100 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 −40 NIS6452 NIS6432 −20 Figure 6. UVLO vs Junction Temperature 40 40 35 35 30 30 RDS(ON) (W) 45 25 20 15 5 3.4 80 100 15 5 3.3 60 20 10 3.2 40 25 10 3.1 20 Figure 7. Vclamp vs Junction Temperature 45 3 0 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) 0 20 POWER (W) Figure 4. Slew Rate vs Cdvdt capacitance for 3.3V and 5V 2 15 10 CAPACITANCE FROM dv/dt PIN TO GND (pF) RDS(ON) (W) −40°C 10 3.5 0 3.6 3 VCC (V) 3.5 4 4.5 5 5.5 VCC (V) Figure 8. RDS(on) vs VCC for NIS6432 Figure 9. RDS(on) vs VCC for NIS6452 www.onsemi.com 7 6 NIS6432, NIS6452 TYPICAL CHARACTERISTICS 60 RDS(ON) (mW) 50 40 30 20 10 0 −40 −20 0 20 40 60 100 80 JUNCTION TEMPERATURE (°C) Figure 10. RDS(on) vs Junction Temperature Figure 11. Slew Rate Control for NIS6432 4 ILOAD = 2 A 3.5 VISENSE (V) 3 2.5 2 1.5 1 0.5 0 3 3.1 3.3 3.2 3.4 3.5 3.6 VCC (V) Figure 13. VISENSE vs VCC for NIS6432 Figure 12. Slew Rate Control for NIS6452 4 4.5 ILOAD = 2 A 3.5 3.5 2.5 VISENSE (V) VISENSE (V) 3 2 1.5 1 3 2.5 2 1.5 1 0.5 0 RISENSE = 1 kW 4 0.5 3 3.5 4 4.5 5 5.5 0 6 0 0.5 1 1.5 2 2.5 3 3.5 VCC (V) LOAD CURRENT (A) Figure 14. VISENSE vs VCC for NIS6452 Figure 15. VISENSE vs Load Current www.onsemi.com 8 4 4.5 NIS6432, NIS6452 TYPICAL CHARACTERISTICS 4 3.5 11 ILOAD = 2 A DC Steady State 10 CURRENT (A) 2 1.5 7 IOL @ RLIM = 15 kW 6 IOL @ RLIM = 25 kW 5 ISC @ RLIM = 5 kW 4 3 1 2 0.5 −20 0 20 40 60 80 1 0 −60 100 ISC @ RLIM = 25 kW −40 0 −20 20 ISC @ RLIM = 15 kW 40 60 80 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 16. VISENSE vs Ambient Temperature Figure 17. ILIM vs RLIM over Ambient Temperature 11 10 IOL 9 CURRENT LIMIT (A) VISENSE (V) 8 2.5 0 −40 IOL @ RLIM = 5 kW 9 3 8 7 6 5 ISC 4 3 2 1 0 0 5 10 15 20 25 30 RLIM (kW) Figure 18. Overload and Short Circuit Current Limit vs RLIM www.onsemi.com 9 100 NIS6432, NIS6452 APPLICATIONS INFORMATION Basic Operation an external switch and then allowed to go high or after the input power has been recycled. This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The output voltage, which is controlled by an internal dv/dt circuit, will slew from 0 V to the rated output voltage in 1.0 ms. The device will remain on as long as the temperature does not exceed the 175°C limit that is programmed into the chip. The internal current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage in the event that the input exceeds the Vclamp level. An internal charge pump provides bias for the gate voltage of the internal n−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. Thermal Protection The NIS64x2 includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175°C, the device will shut down, and remove power from the load. Output power can be restored by either recycling the input power or toggling the enable pin. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. It is not recommended to operate this device above 150°C for extended periods of time. SAS Disable The SAS Disable feature provides a digital interface to control the output of the eFuse. When the SASIN pin is pulled high by any external digital control circuitry the eFuse switches to its off state. When the SASIN pin is pulled low the eFuse output is turned on. All fault conditions will be cleared when the eFuse is reset through the SAS pin. Overvoltage Clamp Reverse Current Protection The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds Vout−clamp, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. The NIS64x2 monitors and protects against reverse current events, which can be the result of a malfunction in the power supply or noise induced in the input voltage rail under certain load characteristics (for example, when the load is largely capacitive). The protection mechanism disables the eFuse’s output and triggers when the reverse current exceeds the preset magnitude and this condition remains for at least 7.5 ms. The NIS64x2 automatically re−enables its output once the input voltage exceeds the output voltage for at least 100 ms. Enable/Fault The Enable/Fault Pin is a multi−function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip. When this pin is low, the output of the fuse will be turned off. When this pin is high the output of the fuse will be turned−on. If a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its tri−state operation, it should not be connected to any type of logic with an internal pull−up device. If the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. This signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. If this pin is tied to another device in this family, a thermal shutdown of one device will cause both devices to disable their outputs. Both devices will turn on once the fault is removed for the auto−retry devices. Since this is a latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with Current Limit The current limit circuit uses a SENSEFET along with a reference and amplifier to control the peak current in the device. The SENSEFET allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor. The current limit circuit has two limiting values, one for short circuit hold current − ISC, another is overload current limit IOL. Refer to Figure 4. for dependence of IOL and ISC vs current limit resistor RLIM. Load Current Monitoring The current monitor ISENSE pin provides a small current proportional to the main device current which is flowing through the device. This pin should have a decoupling capacitor to filter out internal sampling noise. A resistor connected between the ISENSE pin and GND converts the ISENSE current into a GND referenced voltage. This pin can be floated if the feature is not required by application. Connect this pin to ground through 1 kOhm 1% resistor and www.onsemi.com 10 NIS6432, NIS6452 a 1 mF capacitor to ground to read the voltage corresponding to a load current. is approximately 1.0 ms. This pin includes an internal current source of approximately 1 mA. Since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. Aluminum electrolytic capacitors are not recommended for this circuit. Refer to Figure 5. for the typical ramp time vs Cdvdt capacitor. Anytime that the unit shuts down due to a fault, enable shut−down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on. Slew Rate Control The dV/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. An internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. The default ramp time ORDERING INFORMATION Device Input Voltage Marking Auto−Retry/Latch NIS6432MT1TWG 3.3 V 63L Latch NIS6432MT2TWG 3.3 V 63A Auto−Retry NIS6452MT1TWG 5.0 V 65L Latch NIS6452MT2TWG 5.0 V 65A Auto−Retry Package Shipping† 3000 / Tape & Reel WQFN 2x3 (Pb−Free) 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WQFN12 3.0x2.0, 0.5P CASE 510BM ISSUE C SCALE 4:1 DATE 09 DEC 2019 GENERIC MARKING DIAGRAM* XXXXX ALYWG G XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON93408F WQFN12 3.0X2.0, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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