NL17SHT126P5T5G

NL17SHT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The NL17SHT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NL17SHT126 requires the 3−state control input (OE) to be set Low to place the output into the high impedance state. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply. The NL17SHT126 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the NL17SHT126 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • • • • • • • • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C http://onsemi.com MARKING DIAGRAM SOT−953 CASE 527AE R M RM 1 = Specific Device Code = Month Code PIN ASSIGNMENT 1 IN A 2 GND 3 OE 4 OUT Y 5 VCC FUNCTION TABLE TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families A Input OE Input Y Output L H X H H L L H Z These are Pb−Free Devices IN A 1 GND 2 OE 3 ORDERING INFORMATION 5 VCC See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 4 OUT Y Figure 1. Pinout (Top View) OE OUT Y IN A Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 0 1 Publication Order Number: NL17SHT126/D NL17SHT126 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Characteristics −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC + 0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA IOUT DC Output Current ±25 mA ICC DC Supply Current, VCC and GND 50 mA PD Power Dissipation in Still Air 50 mW TL Lead Temperature, 1 mm from Case for 10 s 260 °C TJ Junction Temperature Under Bias +150 °C Tstg Storage Temperature −65 to +150 °C ILatchup Latchup Performance ±100 mA VOUT < GND; VOUT > VCC Above VCC and Below GND at 125°C (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VCC DC Supply Voltage 3.0 5.5 V VIN DC Input Voltage 0.0 5.5 V DC Output Voltage 0.0 VCC V −55 +125 °C 0 20 ns/V VOUT TA Operating Temperature Range tr, tf Input Rise and Fall Time VCC = 5.0 V ± 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80 ° C 117.8 TJ = 90 ° C 1,032,200 TJ = 100 ° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130 ° C Junction Temperature °C NORMALIZED FAILURE RATE Device Junction Temperature versus Time to 0.1% Bond Failures 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 NL17SHT126 DC ELECTRICAL CHARACTERISTICS Min 1.4 2.0 2.0 Symbol Parameter VIH Minimum High−Level Input Voltage 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Test Conditions TA = 25°C VCC (V) Typ TA ≤ 85°C Max Min 0.53 0.8 0.8 VIN = VIH or VIL IOH = − 50 mA 3.0 4.5 2.9 4.4 VIN = VIH or VIL IOH = − 4 mA IOH = − 8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA Max 1.4 2.0 2.0 3.0 4.5 0.0 0.0 −55 ≤ TA ≤ 125°C Min Max 1.4 2.0 2.0 0.53 0.8 0.8 V 0.53 0.8 0.8 2.9 4.4 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA ICCT Quiescent Supply Current Input: VIN = 3.4 V Other Input: VCC or GND 5.5 1.35 1.50 1.65 mA IOPD Output Leakage Current VOUT = 5.5 V 0.0 0.5 5.0 10 mA Maximum 3−State Leakage Current VIN = VIH or VIL VOUT = VCC or GND 5.5 ± 0.25 ± 2.5 ± 2.5 mA IOZ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ −55 ≤ TA ≤ 125°C Max Min Max CL = 15pF CL = 50pF 5.6 8.1 8.0 11.5 1.0 1.0 9.5 13.0 12.0 16.0 VCC = 5.0 ± 0.5 V CL = 15pF CL = 50pF 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 8.5 10.5 Maximum Output Enable TIme,OE to Y (Figures 4 and 5) VCC = 3.3 ± 0.3 V RL = RI = 500 W CL = 15pF CL = 50pF 5.4 7.9 8.0 11.5 1.0 1.0 9.5 13.0 11.5 15.0 VCC = 5.0 ± 0.5 V RL = RI = 500 W CL = 15pF CL = 50pF 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 7.5 9.5 Maximum Output Disable Time,OE to Y (Figures 4 and 5) VCC = 3.3 ± 0.3 V RL = RI = 500 W CL = 15pF CL = 50pF 6.5 8.0 9.7 13.2 1.0 1.0 11.5 15.0 14.5 18.0 VCC = 5.0 ± 0.5 V RL = RI = 500 W CL = 15pF CL = 50pF 4.8 7.0 6.8 8.8 1.0 1.0 8.0 10.0 10.0 12.0 10 10 10 VCC = 3.3 ± 0.3 V Min TA ≤ 85°C Typ Parameter Maximum Propagation Delay, A to Y (Figures 3 and 5) Test Conditions Cin Maximum Input Capacitance 4 Cout Maximum Three−State Output Capacitance (Output in High Impedance State) 6 CPD Power Dissipation Capacitance (Note 2) Min Max Unit ns ns ns pF pF Typical @ 25°C, VCC = 5.0 V 14 pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per buffer). CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. http://onsemi.com 3 NL17SHT126 SWITCHING WAVEFORMS VCC OE 50% VCC GND 50% A tPZL GND tPHL tPLH tPLZ HIGH IMPEDANCE 50% VCC Y 50% VCC tPZH VOL + 0.3V tPHZ Y VOH - 0.3V 50% VCC Y Figure 4. Switching Waveforms Figure 5. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST HIGH IMPEDANCE DEVICE UNDER TEST CL* *Includes all probe and jig capacitance OUTPUT 1 kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 6. Test Circuit Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit ORDERING INFORMATION Device NL17SHT126P5T5G Package Shipping† SOT−953 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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