DATA SHEET
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Dual Unbuffered Inverter
MARKING
DIAGRAMS
6
NL27WZU04
The NL27WZU04 is a high performance dual unbuffered inverter
operating from a 1.65 to 5.5 V supply.
SC−88
DF SUFFIX
CASE 419B
1
XXXM G
G
1
Features
•
•
•
•
•
•
•
•
•
Designed for 1.65 V to 5.5 V VCC Operation
Input Overvoltage Tolerant up to 5.5 V
IOFF Supports Partial Power Down Protection
Source/Sink 24 mA at 3.0 V
Source/Sink 12 mA at 3.0 V (NLV)
Available in SC−88, SC−74, TSOP−6 and UDFN6 Packages
Chip Complexity < 100 FETs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A1
1
Y1
A2
1
Y2
SC−74
CASE318F−05
6
1
TSOP−6
CASE 318G−02
1
1
XXX MG
G
1
UDFN6
1.45 x 1.0
CASE 517AQ
UDFN6
1.0 x 1.0
CASE 517BX
X, XXX
M
A
Y
W
G
Figure 1. Logic Symbol
XXX MG
G
XM
XM
1
= Specific Device Code
= Date Code*
=Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
April, 2022 − Rev. 13
1
Publication Order Number:
NL27WZU04/D
NL27WZU04
A1
A1
1
6
Y1
GND
2
5
VCC
A2
3
4
Y2
Y1
1
6
GND
2
5
VCC
A2
3
4
Y2
(SC−88 / SC−74 / TSOP−6)
UDFN6
Figure 2. Pinout (Top View)
PIN ASSIGNMENT
FUNCTION TABLE
A Input
Y Output
A1
L
H
2
GND
H
L
3
A2
4
Y2
5
VCC
6
Y1
Pin
Function
1
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2
NL27WZU04
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
SC−88 (NLV), TSOP−6
SC−88, SC−74, UDFN6
−0.5 to +7.0
−0.5 to +6.5
V
VIN
DC Input Voltage
SC−88 (NLV), TSOP−6
SC−88, SC−74, UDFN6
−0.5 to +7.0
−0.5 to +6.5
V
−0.5 to VCC + 0.5
V
VOUT
Characteristics
DC Output Voltage
IIK
DC Input Diode Current
−50
mA
IOK
DC Output Diode Current
±50
mA
IOUT
DC Output Source/Sink Current
±50
mA
DC Supply Current per Supply Pin or Ground Pin
±100
mA
−65 to +150
°C
ICC or IGND
TSTG
VIN < GND
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 secs
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
SC−88
SC−74
UDFN6
377
320
154
°C/W
PD
Power Dissipation in Still Air
SC−88
SC−74
UDFN6
332
300
812
mW
Level 1
−
UL 94 V−0 @ 0.125 in
−
Human Body Model
Charged Device Model
(NLV) Charged Device Model
2000
1000
N/A
V
(NLV)
±500
±100
mA
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
Oxygen Index: 28 to 34
ESD Withstand Voltage (Note 3)
Latchup Performance (Note 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10mm−by−1inch, 2 ounce copper trace no air flow per JESD51−7.
3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.
4. Tested to EIA/JESD78 Class II.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
1.65
5.5
V
V
VCC
Positive DC Supply Voltage
VIN
DC Input Voltage
0
5.5
DC Output Voltage
0
VCC
−55
+125
°C
0
0
0
0
20
20
10
5
ns/V
VOUT
TA
tr , tf
Operating Temperature Range
Input Rise and Fall Time
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
NL27WZU04
DC ELECTRICAL CHARACTERISTICS
TA = 255C
−555C 3 TA 3 1255C
VCC
(V)
Min
Typ
Max
Min
Max
Units
High−Level Input
Voltage
1.65 to 1.95
0.85 VCC
−
−
0.85 VCC
−
V
2.3 to 5.5
0.80 VCC
−
−
0.80 VCC
−
Low−Level Input
Voltage
1.65 to 1.95
−
−
0.15 VCC
−
0.15 VCC
2.3 to 5.5
−
−
0.20 VCC
−
0.20 VCC
1.65 to 5.5
VCC − 0.1
VCC
−
VCC − 0.1
−
VIN = GND
IOH = −3 mA
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
1.65
2.3
2.7
3.0
3.0
4.5
1.29
1.9
2.2
2.4
2.3
3.8
1.52
2.1
2.3
2.6
2.5
4.2
−
−
−
−
−
−
1.29
1.9
2.2
2.4
2.3
3.8
−
−
−
−
−
−
High−Level Output
Voltage
VIN = GND
IOH = −100 mA
IOH = −4 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
VCC
1.4
2.1
2.4
2.7
2.5
4.0
−
−
−
−
−
−
−
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
−
−
−
−
−
−
−
Low−Level Output
Voltage (NLV)
VIN = VIH
IOL = 100 mA
1.65 to 5.5
−
−
0.1
−
0.1
VIN = VCC
IOL = 3 mA
IOL = 4 mA
IOL = 6 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
1.65
2.3
2.7
3.0
3.0
4.5
−
−
−
−
−
−
0.08
0.2
0.2
0.24
0.26
0.31
0.24
0.3
0.4
0.4
0.55
0.55
−
−
−
−
−
−
0.24
0.3
0.4
0.4
0.55
0.55
Low−Level Output
Voltage
VIN = VCC
IOL = 100 mA
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
−
−
−
−
−
−
−
−
0.08
0.2
0.22
0.28
0.38
0.42
0.1
0.24
0.3
0.4
0.4
0.55
0.55
−
−
−
−
−
−
−
0.1
0.24
0.3
0.4
0.4
0.55
0.55
Input Leakage Current
VIN = 5.5 V or GND
1.65 to 5.5
−
−
±0.1
−
±1.0
mA
IOFF
Power Off Leakage
Current
VIN = 5.5 V
0
−
−
1.0
−
10
mA
ICC
Quiescent Supply
Current
VIN = VCC or GND
5.5
−
−
1.0
−
10
mA
Symbol
VIH
VIL
VOH
VOL
IIN
Parameter
High−Level Output
Voltage (NLV)
Condition
VIN = VIH or VIL
IOH = −100 mA
V
V
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NL27WZU04
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
tPLH
tPHL
Condition
VCC (V)
Min
Typ
Max
Min
Max
Units
RL = 1 MW, CL = 15 pF
1.65 to 1.95
−
5.5
9.8
−
11.0
ns
RL = 1 MW, CL = 15 pF
2.3 to 2.7
−
3.3
5.7
−
6.3
RL = 1 MW, CL = 15 pF
3.0 to 3.6
−
2.7
4.1
−
4.5
−
4.0
6.4
−
7.0
−
2.2
3.3
−
3.6
−
3.4
5.6
−
6.2
Parameter
Propagation Delay
Input A to Y
(Figure 3 and 4)
*55°C 3 TA 3 125°C
RL = 500 W, CL = 50 pF
RL = 1 MW, CL = 15 pF
4.5 to 5.5
RL = 500 W, CL = 50 pF
CAPACITIVE CHARACTERISTICS
Symbol
CIN
Parameter
Condition
Typical
Units
Input Capacitance
VCC = 5.5 V, VIN = 0 V or VCC
2.5
pF
COUT
Output Capacitance
VCC = 5.5 V, VIN = 0 V or VCC
4.0
pF
CPD
Power Dissipation Capacitance
(Note 5)
10 MHz, VCC = 5.5 V, VIN = 0 V or VCC
4.0
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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5
NL27WZU04
OPEN
2 x VCC
Test
Switch
Position
tPLH / tPHL
Open
tPLZ / tPZL
2 x VCC
50
500
500
tPHZ / tPZH
GND
50
500
500
GND
R1
OUTPUT
DUT
RL
RT
CL, pF
RL, W
R1 , W
See AC Characteristics Table
X = Don’t Care
CL *
CL includes probe and jig capacitance
RT is ZOUT of pulse generator (typically 50 W)
f = 1 MHz
Figure 3. Test Circuit
tr = 3 ns
tf = 3 ns
90%
90%
Vmi
INPUT
Vmi
INPUT
Vmi
10%
10%
tPHL
Vmi
GND
GND
tPZL
tPLH
Vmo
OUTPUT
VCC
VCC
tPLZ
~VCC
VOH
Vmo
OUTPUT
Vmo
VOL + VY
VOL
VOL
tPLH
OUTPUT
tPHL
Vmo
tPZH
VOH
Vmo
tPHZ
VOH
VOH − VY
Vmo
OUTPUT
VOL
~0 V
Figure 4. Switching Waveforms
Vmo, V
VCC, V
Vmi, V
tPLH, tPHL
1.65 to 1.95
VCC/2
VCC/2
VCC/2
0.15
2.3 to 2.7
VCC/2
VCC/2
VCC/2
0.15
3.0 to 3.6
VCC/2
VCC/2
VCC/2
0.3
4.5 to 5.5
VCC/2
VCC/2
VCC/2
0.3
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6
tPZL, tPLZ, tPZH, tPHZ
VY, V
NL27WZU04
DEVICE ORDERING INFORMATION
Packages
Specific Device Code
Pin 1 Orientation
(See below)
Shipping†
NL27WZU04DFT2G
SC−88
M6
Q4
3000 / Tape & Reel
NL27WZU04DFT2G−L22348**
SC−88
M6
Q4
3000 / Tape & Reel
NLV27WZU04DFT2G*
SC−88
M6
Q4
3000 / Tape & Reel
NL27WZU04DBVT1G
SC−74
M6
Q4
3000 / Tape & Reel
NL27WZU04DTT1G**
TSOP−6
M6
Q4
3000 / Tape & Reel
NL27WZU04MU1TCG
(In Development)
UDFN6, 1.45 x 1.0, 0.5P
TBD
Q4
3000 / Tape & Reel
NL27WZU04MU3TCG
(In Development)
UDFN6, 1.0 x 1.0, 0.35P
TBD
Q4
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**Please refer to NLV specifications for this device.
Pin 1 Orientation in Tape and Reel
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7
NL27WZU04
PACKAGE DIMENSIONS
UDFN6, 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
A
B
D
L
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
L1
PIN ONE
REFERENCE
0.10 C
ÉÉÉ
ÉÉÉ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
0.10 C
DETAIL B
MOLD CMPD
DETAIL B
0.05 C
6X
DIM
A
A1
A2
b
D
E
e
L
L1
OPTIONAL
CONSTRUCTIONS
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.07 REF
0.20
0.30
1.45 BSC
1.00 BSC
0.50 BSC
0.30
0.40
−−−
0.15
MOUNTING FOOTPRINT
0.05 C
A1
SIDE VIEW
A2
e
6X
C
6X
SEATING
PLANE
L
1.24
3
1
DETAIL A
6X
0.53
6
0.30
PACKAGE
OUTLINE
4
BOTTOM VIEW
6X
0.50
PITCH
DIMENSIONS: MILLIMETERS
b
0.10 C A B
0.05 C
1
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
NOTE 3
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11
NL27WZU04
PACKAGE DIMENSIONS
UDFN6, 1x1, 0.35P
CASE 517BX
ISSUE O
PIN ONE
REFERENCE
2X
0.08 C
2X
ÉÉÉ
ÉÉÉ
0.08 C
0.05 C
L1
A B
D
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
L3
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
ÉÉ
ÉÉ
ÇÇ
TOP VIEW
EXPOSED Cu
DETAIL B
A3
A1
MOLD CMPD
DETAIL B
A
ALTERNATE
CONSTRUCTION
0.05 C
SIDE VIEW
C
SEATING
PLANE
3
1
6X
MILLIMETERS
MIN
MAX
0.50
0.65
0.00
0.05
0.13 REF
0.17
0.23
1.00 BSC
1.00 BSC
0.35
0.20
0.40
−−−
0.15
0.26
0.33
RECOMMENDED
SOLDERING FOOTPRINT*
e
DETAIL A
DIM
A
A1
A3
b
D
E
e
L
L1
L3
L
6X
0.25
6X
0.52
1.20
6
4
BOTTOM VIEW
6X
PACKAGE
OUTLINE
b
0.07
M
C A B
0.05
M
C
1
0.35
PITCH
NOTE 3
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−74
CASE 318F
ISSUE P
6
1
SCALE 2:1
DATE 07 OCT 2021
GENERIC
MARKING DIAGRAM*
XXX MG
G
XXX
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 1:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. ANODE
6. CATHODE
STYLE 2:
PIN 1. NO CONNECTION
2. COLLECTOR
3. EMITTER
4. NO CONNECTION
5. COLLECTOR
6. BASE
STYLE 3:
PIN 1. EMITTER 1
2. BASE 1
3. COLLECTOR 2
4. EMITTER 2
5. BASE 2
6. COLLECTOR 1
STYLE 4:
PIN 1. COLLECTOR 2
2. EMITTER 1/EMITTER 2
3. COLLECTOR 1
4. EMITTER 3
5. BASE 1/BASE 2/COLLECTOR 3
6. BASE 3
STYLE 5:
PIN 1. CHANNEL 1
2. ANODE
3. CHANNEL 2
4. CHANNEL 3
5. CATHODE
6. CHANNEL 4
STYLE 7:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 8:
PIN 1. EMITTER 1
2. BASE 2
3. COLLECTOR 2
4. EMITTER 2
5. BASE 1
6. COLLECTOR 1
STYLE 9:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 10:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 11:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42973B
SC−74
STYLE 6:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
SEATING
PLANE
C
DETAIL Z
e
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
1
IC
0.95
XXX MG
G
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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