NL7SZ57DFT2G

DATA SHEET www.onsemi.com Configurable Multifunction Gate NL7SZ57 MARKING DIAGRAMS 6 The NL7SZ57 is an advanced high−speed CMOS multifunction gate. The device allows the user to choose logic functions AND, OR, NAND, NOR, XNOR, INVERT and BUFFER. The device has Schmitt−trigger inputs, thereby enhancing noise immunity. • Designed for 1.65 V to 5.5 V VCC Operation 3.3 ns tPD at VCC = 5 V (Typ) Inputs/Outputs Overvoltage Tolerant up to 5.5 V IOFF Supports Partial Power Down Protection Sink 24 mA at 3.0 V Chip Complexity < 100 FETs NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant XXXMG G 1 6 Features • • • • • • • 1 SC−88/SC70−6/ SOT−363 CASE 419B−02 1 1 SC−74 CASE 318F−05 XXX MG G 1 UDFN6, 1.45x1.0, 0.5P CASE 517AQ UDFN6, 1x1, 0.35P CASE 517BX XM XM 1 XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location or may not be present) *Date Code orientation and/or position may vary depending upon manufacturing location. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 July, 2022 − Rev. 5 1 Publication Order Number: NL7SZ57/D NL7SZ57 B 1 6 C GND 2 5 VCC A 3 4 Y B 1 6 C GND 2 5 VCC A 3 4 Y UDFN6 (SC−88 / SC−74) Figure 1. Pinout (Top View) A Y B C Figure 2. Function Diagram PIN ASSIGNMENT FUNCTION TABLE* Pin Function Input Output 1 B A B C Y 2 GND L L L H 3 A L L H L 4 Y L H L H 5 VCC L H H H 6 C H L L L H L H L H H L L H H H H *To select a logic function, please refer to “Logic Configurations section”. www.onsemi.com 2 NL7SZ57 LOGIC CONFIGURATIONS B C B C VCC Y B Y 1 6 2 5 3 4 VCC B C Y C B Y Y C Figure 3. 2−Input AND (When A = “H”) B 1 6 2 5 3 4 C Y Figure 4. 2−Input NAND with input B inverted (When A = “L”) VCC VCC A C A C A Y A Y 1 6 2 5 3 4 C Y C A Y C Figure 5. 2−Input NAND with Input C Inverted (When B = “H”) A Y 1 6 2 5 3 4 C B Y 1 6 2 5 3 4 VCC C A Y A Y Figure 7. 2−Input XNOR (When A = B) 1 6 2 5 3 4 Y Figure 8. Inverter (When B = C = “L”) VCC B B Y Figure 6. 2−Input NOR (When B = “L”) VCC B C Y 1 6 2 5 3 4 Y Figure 9. Buffer (When A = “L” and C = “H”) www.onsemi.com 3 NL7SZ57 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage (NLV) −0.5 to +7.0 −0.5 to +6.5 V VIN DC Input Voltage (NLV) −0.5 to +7.0 −0.5 to +6.5 V VOUT Parameter DC Output Voltage (NLV) Active−Mode (High or Low State) Tri−State Mode (Note 1) Power−Down Mode (VCC = 0 V) −0.5 to VCC + 0.5 −0.5 to +7.0 −0.5 to +7.0 V DC Output Voltage Active−Mode (High or Low State) Tri−State Mode (Note 1) Power−Down Mode (VCC = 0 V) −0.5 to VCC + 0.5 −0.5 to +6.5 −0.5 to +6.5 V VIN < GND −50 mA VOUT < GND −50 mA IIK DC Input Diode Current IOK DC Output Diode Current IOUT DC Output Source/Sink Current $50 mA DC Supply Current per Supply Pin or Ground Pin $100 mA −65 to +150 °C 260 °C ICC or IGND TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Secs TJ Junction Temperature Under Bias +150 °C qJA Thermal Resistance (Note 2) SC−88 SC−74 UDFN6 377 320 154 °C/W PD Power Dissipation in Still Air SC−88 SC−74 UDFN6 332 390 812 mW MSL FR VESD ILATCHUP Moisture Sensitivity Level 1 Flammability Rating Oxygen Oxygen Index: 28 to 34 ESD Withstand Voltage (Note 3) UL 94 V−0 @ 0.125 in Human Body Mode Charged Device Model (NLV) Charged Device Model >2000 >200 N/A V (NLV) $500 $100 mA Latchup Performance (Note 4) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Applicable to devices with outputs that may be tri−stated. 2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow per JESD51−7. 3. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A. 4. Tested to EIA/JESD78 Class II. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Positive DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage TA Operating Free−Air Temperature tr, tf Input Rise or Fall Rate Active−Mode (High or Low State) Tri−State Mode (Note 1) Power−Down Mode (VCC = 0 V) VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V Min Max Unit 1.65 5.5 V 0 5.5 V 0 0 0 VCC 5.5 5.5 V −55 +125 °C 0 0 0 0 No Limit No Limit No Limit No Limit nS/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 NL7SZ57 DC ELECTRICAL CHARACTERISTICS Symbol VT+ Parameter Condition Positive Input Threshold Voltage (NLV) Positive Input Threshold Voltage VT− Negative Input Threshold Voltage (NLV) Negative Input Threshold Voltage VH Negative Input Threshold Voltage (NLV) Negative Input Threshold Voltage VOH −405C v TA v 855C TA = 255C −555C v TA v 1255C VCC (V) Min Typ Max Min Max Min Max Unit 1.65 0.79 − 1.16 − 1.16 − 1.16 V 2.3 1.11 − 1.56 − 1.56 − 1.56 3.0 1.5 − 1.87 − 1.87 − 1.87 4.5 2.16 − 2.74 − 2.74 − 2.74 5.5 2.61 − 3.33 − 3.33 − 3.33 1.65 − − 1.4 − 1.4 − 1.4 2.3 − − 1.8 − 1.8 − 1.8 3.0 − − 2.2 − 2.2 − 2.2 4.5 − − 3.1 − 3.1 − 3.1 5.5 − − 3.6 − 3.6 − 3.6 1.65 0.35 − 0.62 0.35 − 0.35 − 2.3 0.58 − 0.87 0.58 − 0.58 − 3.0 0.84 − 1.19 0.84 − 0.84 − 4.5 1.41 − 1.9 1.41 − 1.41 − 5.5 1.78 − 2.2 1.78 − 1.78 − 1.65 0.2 − − 0.2 − 0.2 − 2.3 0.4 − − 0.4 − 0.4 − 3.0 0.6 − − 0.6 − 0.6 − 4.5 1.0 − − 1.0 − 1.0 − 5.5 1.2 − − 1.2 − 1.2 − 1.65 0.3 − 0.62 0.3 0.62 0.3 0.62 2.3 0.4 − 0.8 0.4 0.8 0.4 0.8 3.0 0.53 − 0.87 0.53 0.87 0.53 0.87 4.5 0.71 − 1.04 0.71 1.04 0.71 1.04 5.5 0.8 − 1.2 0.8 1.2 0.8 1.2 1.65 0.1 0.1 0.9 0.48 0.9 0.1 0.9 2.3 0.25 0.25 1.1 0.75 1.1 0.25 1.1 3.0 0.4 0.4 1.2 0.93 1.2 0.4 1.2 4.5 0.6 0.6 1.5 1.2 1.5 0.6 1.5 5.5 0.7 0.7 1.7 1.4 1.7 0.7 1.7 High−Level Output Voltage IOH = −50 mA 1.65 to 5.5 VCC − 0.1 VCC − VCC − 0.1 − VCC − 0.1 − VIN = VIH or VIL IOH = −4 mA 1.65 1.20 1.52 − 1.20 − 1.20 − IOH = −8 mA 2.3 1.9 2.1 − 1.9 − 1.9 − IOH = −16 mA 3 2.4 2.7 − 2.4 − 2.4 − IOH = −24 mA 3 2.3 2.5 − 2.3 − 2.3 − IOH = −32 mA 4.5 3.8 4 − 3.8 − 3.8 − www.onsemi.com 5 V V V V V V NL7SZ57 DC ELECTRICAL CHARACTERISTICS Symbol VOL IIN Parameter Condition −405C v TA v 855C TA = 255C VCC (V) −555C v TA v 1255C Min Typ Max Min Max Min Max Unit 1.65 to 5.5 − − 0.1 − 0.1 − 0.1 V Low−Level Output Voltage IOL = 100 mA VIN = VIH or VIL IOL = 4 mA 1.65 − 0.08 0.45 − 0.45 − 0.45 IOL = 8 mA 2.3 − 0.2 0.3 − 0.3 − 0.4 IOL = 16 mA 3 − 0.28 0.4 − 0.4 − 0.5 IOL = 24 mA 3 − 0.38 0.55 − 0.55 − 0.55 IOL = 32 mA 4.5 − 0.42 0.55 − 0.55 − 0.65 Input Leakage Current VIN = 5.5 V or GND 1.65 to 5.5 − − +0.1 − +1.0 − +1.0 mA IOFF Power Off Leakage Current VIN = 5.5 V or VOUT = 5.5 V 0 − − 1.0 − 10 − 10 mA ICC Quiescent Supply Current VIN = 5.5 V or GND 5.5 − − 1.0 − 10 − 10 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS TA = 255C Symbol Parameter tPLH, tPHL Propagation Delay, (A or B or C) to Y (Figures 10 and 11) −405C v TA v 855C −555C v TA v 1255C VCC (V) Min Typ Max Min Max Min Max Unit RL = 1 kW, CL = 30 pF 1.65 to 1.95 − 8.6 14.4 − 14.4 − 14.4 ns RL = 500 W, CL = 30 pF 2.3 to 2.7 − 5.1 8.3 − 8.3 − 8.3 RL = 500 W, CL = 50 pF 3.0 to 3.6 − 3.9 6.3 − 6.3 − 6.3 4.5 to 5.5 − 3.3 5.1 − 5.1 − 5.1 Condition CAPACITIVE CHARACTERISTICS Symbol CIN Parameter Condition Typical Unit Input Capacitance VCC = 5.5 V, VIN = 0 V or VCC 2.5 pF COUT Output Capacitance VCC = 5.5 V, VIN = 0 V or VCC 4.0 pF CPD Power Dissipation Capacitance (Note 5) 10 MHz, VCC = 3.3 V, VIN = 0 V or VCC 10 MHz, VCC = 5.0 V, VIN = 0 V or VCC 16 19.5 pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD • VCC2 • fin + ICC • VCC. www.onsemi.com 6 NL7SZ57 OPEN 2 x VCC Test Switch Position tPLH / tPHL Open tPLZ / tPZL 2 x VCC 50 500 500 tPHZ / tPZH GND 50 500 500 GND R1 OUTPUT DUT RL RT CL, pF RL, W R1 , W See AC Characteristics Table X = Don’t Care CL * CL includes probe and jig capacitance RT is ZOUT of pulse generator (typically 50 W) f = 1 MHz Figure 10. Test Circuit tr = 3 ns tf = 3 ns 90% 90% Vmi INPUT Vmi INPUT Vmi 10% 10% tPHL Vmi GND GND tPZL tPLH Vmo OUTPUT VCC VCC tPLZ ~VCC VOH Vmo OUTPUT Vmo VOL + VY VOL VOL tPLH OUTPUT tPHL Vmo tPZH VOH Vmo tPHZ VOH VOH − VY Vmo OUTPUT VOL ~0 V Figure 11. Switching Waveforms Vmo, V VCC, V Vmi, V tPLH, tPHL tPZL, tPLZ, tPZH, tPHZ VY, V 1.65 to 1.95 VCC / 2 VCC / 2 VCC / 2 0.15 2.3 to 2.7 VCC / 2 VCC / 2 VCC / 2 0.15 3.0 to 3.6 VCC / 2 VCC / 2 VCC / 2 0.3 4.5 to 5.5 VCC / 2 VCC / 2 VCC / 2 0.3 www.onsemi.com 7 NL7SZ57 ORDERING INFORMATION Package Specific Device Code Pin 1 Orientation (See below) NL7SZ57DFT2G SC−88 (Pb−Free) MN Q4 3000 / Tape & Reel NL7SZ57DFT2G−L22348** SC−88 (Pb−Free) MN Q4 3000 / Tape & Reel NLV7SZ57DFT2G* SC−88 (Pb−Free) MN Q4 3000 / Tape & Reel NL7SZ57DBVT1G SC−74 (Pb−Free) AL Q4 3000 / Tape & Reel NL7SZ57MU1TCG (In Development) UDFN6, 1.45 x 1.0, 0.5P (Pb−Free) TBD Q4 3000 / Tape & Reel NL7SZ57MU3TCG (In Development) UDFN6, 1.0 x 1.0, 0.35P (Pb−Free) P (Rotated 270° CW) Q4 3000 / Tape & Reel Device Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. ** Please refer to NLV specifications for this device. Pin 1 Orientation in Tape and Reel www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−74 CASE 318F ISSUE P 6 1 SCALE 2:1 DATE 07 OCT 2021 GENERIC MARKING DIAGRAM* XXX MG G XXX M G = Specific Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLE 1: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. ANODE 6. CATHODE STYLE 2: PIN 1. NO CONNECTION 2. COLLECTOR 3. EMITTER 4. NO CONNECTION 5. COLLECTOR 6. BASE STYLE 3: PIN 1. EMITTER 1 2. BASE 1 3. COLLECTOR 2 4. EMITTER 2 5. BASE 2 6. COLLECTOR 1 STYLE 4: PIN 1. COLLECTOR 2 2. EMITTER 1/EMITTER 2 3. COLLECTOR 1 4. EMITTER 3 5. BASE 1/BASE 2/COLLECTOR 3 6. BASE 3 STYLE 5: PIN 1. CHANNEL 1 2. ANODE 3. CHANNEL 2 4. CHANNEL 3 5. CATHODE 6. CHANNEL 4 STYLE 7: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 8: PIN 1. EMITTER 1 2. BASE 2 3. COLLECTOR 2 4. EMITTER 2 5. BASE 1 6. COLLECTOR 1 STYLE 9: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 10: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 11: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR DOCUMENT NUMBER: DESCRIPTION: 98ASB42973B SC−74 STYLE 6: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative