NL7SZ97

NL7SZ97 Configurable Multifunction Gate The NL7SZ97 is an advanced high−speed CMOS multifunction gate. The device allows the user to choose logic functions MUX, AND, OR, NAND, NOR, INVERT and BUFFER. The device has Schmitt−trigger inputs, thereby enhancing noise immunity. The NL7SZ97 input and output structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage. Features http://onsemi.com • • • • • • • High Speed: tPD = 3.3 ns (Typ) @ VCC = 5.0 V Low Power Dissipation: ICC = 1 mA (Maximum) at TA = 25°C Power Down Protection Provided on inputs Balanced Propagation Delays Overvoltage Tolerant (OVT) Input and Output Pins Ultra−Small Package This is a Pb−Free Device 1 SC−88 (SOT−363) CASE 419B MARKING DIAGRAM 6 MK MG G 1 MK = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENTS IN B 1 6 IN C GND 2 5 VCC IN A 3 (Top View) 4 OUT Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 3 1 Publication Order Number: NL7SZ97/D NL7SZ97 IN A OUT Y IN B IN C Figure 1. Function Diagram PIN ASSIGNMENT 1 2 3 4 5 6 IN B GND IN A OUT Y VCC IN C A L L L L H H H H FUNCTION TABLE* Input B L L H H L L H H C L H L H L H L H Output Y L L H L L H H H *To select a logic function, please refer to “Logic Configurations section”. http://onsemi.com 2 NL7SZ97 LOGIC CONFIGURATIONS VCC B A C Y A B 1 2 3 6 5 4 Y C A C 1 Y A 2 3 6 5 4 Y VCC C Figure 2. 2−Input MUX Figure 3. 2−Input AND (When B = “L”) VCC VCC A C A C Y A Y 1 2 3 6 5 4 Y C B C B C Y B 1 2 Y 3 6 5 4 Y C Figure 4. 2−Input OR with Input C Inverted (When B = “H”) VCC Figure 5. 2−Input AND with Input C Inverted (When A = “L”) VCC B C B Y 1 2 3 6 5 4 C C Y Y 1 2 3 6 5 4 C Y Figure 6. 2−Input OR (When A =”H”) Figure 7. Inverter (When A = “L” and B = “H”) VCC B B Y 1 2 3 6 5 4 Y Figure 8. Buffer (When A = C = “L”) http://onsemi.com 3 NL7SZ97 MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1) Power Dissipation in Still Air at 85°C Moisture Sensitivity Flammability Rating Oxygen ESD Withstand Voltage Index: 28 to 34 Human Body Mode (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) SC−88 SC−88 VIN < GND VOUT < GND Parameter Value −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −50 −50 $50 $100 $100 −65 to +150 260 +150 350 200 Level 1 UL 94 V−0 @ 0.125 in >2000 >200 N/A $500 V Unit V V V mA mA mA mA mA °C °C °C °C/W mW ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 5) mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm2 by 1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA Dt/DV Positive DC Supply Voltage Digital Input Voltage Output Voltage Operating Free−Air Temperature (Note 6) Input Transition Rise or Fall Rate VCC = 2.5 V $ 0.2 V VCC = 3.3 V $ 0.3 V VCC = 5.0 V $ 0.5 V Parameter Min 1.65 0 0 −55 0 0 0 Max 5.5 5.5 5.5 +125 No Limit No Limit No Limit Unit V V V °C nS/V 6. The NL7SZ97 will not have degradation in its electrical spcifications or Mean−Time−Between−Failure (MTBF) when exposed to a temperature cycle test of 140°C for 21 hours, 135°C for 750 hours and of 130°C for 175 hours. http://onsemi.com 4 NL7SZ97 DC ELECTRICAL CHARACTERISTICS VCC (V) 1.65 2.3 3.0 4.5 5.5 VT− Negative Threshold Voltage 1.65 2.3 3.0 4.5 5.5 VH Hysteresis Voltage 1.65 2.3 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN v VT−MIN IOH = −50 mA VIN v VT−MIN IOH = −4 mA IOH = −8 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA VOL Maximum Low−Level Output Voltage VIN w VT+MAX IOL = 50 mA VIN w VT+MAX IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA IIN ICC Input Leakage Current Quiescent Supply Current 0 v VIN v 5.5 V 0 v VIN v VCC 1.65 2.3 3.0 3.0 4.5 0 to 5.5 5.5 0.45 0.3 0.4 0.55 0.55 $0.1 1.0 0.45 0.3 0.4 0.55 0.55 $1.0 10 0.45 0.3 0.4 0.55 0.55 $1.0 10 mA mA 1.65 2.3 3.0 3.0 4.5 1.65 − 5.5 1.2 1.9 2.4 2.3 3.8 0.1 1.2 1.9 2.4 2.3 3.8 0.1 1.2 1.9 2.4 2.3 3.8 0.1 V 1.65 − 5.5 TA = 255C Min 0.79 1.11 1.5 2.16 2.61 0.35 0.58 0.84 1.41 1.78 0.30 0.40 0.53 0.71 0.8 VCC − 0.1 Typ Max 1.16 1.56 1.87 2.74 3.33 0.62 0.87 1.19 1.9 2.29 0.62 0.8 0.87 1.04 1.2 0.35 0.58 0.84 1.41 1.78 0.30 0.40 0.53 0.71 0.8 VCC − 0.1 0.62 0.8 0.87 1.04 1.2 TA v +855C Min Max 1.16 1.56 1.87 2.74 3.33 0.35 0.58 0.84 1.41 1.78 0.30 0.40 0.53 0.71 0.8 VCC − 0.1 0.62 0.8 0.87 1.04 1.2 V V TA = −555C to +1255C Min Max 1.16 1.56 1.87 2.74 3.33 V Unit V Symbol VT+ Parameter Positive Threshold Voltage Conditions http://onsemi.com 5 NL7SZ97 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 255C Symbol tPLH, tPHL Parameter Propagation Delay, Any Input to Output Y (See Test Circuit) VCC (V) 1.65 − 1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 CIN CPD Input Capacitance Power Dissipation Capacitance (Note 7) 5.0 f = 10 MHz Test Condition Min 3.2 2.0 1.5 1.1 Typ 8.6 5.1 3.9 3.3 3.5 22 Max 14.4 8.3 6.3 5.1 TA v +855C Min 3.2 2.0 1.5 1.1 Max 14.4 8.3 6.3 5.1 TA = −555C to +1255C Min 3.2 2.0 1.5 1.1 Max 14.4 8.3 6.3 5.1 pF pF Unit ns 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. TEST CIRCUIT AND VOLTAGE WAVEFORMS From Output Under Test RL VLOAD Open GND CL * RL Test tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND *CL includes probes and jig capacitance. Figure 9. Load Circuit Inputs VCC 1.8 V $ 0.15 V 2.5 V $ 0.2 V 3.3 V $ 0.3 V 5.5 V $ 0.5 V VI VCC VCC 3V VCC tr/tf v 2 ns v 2 ns v 2.5 ns v 2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 x VCC 2 x VCC 6V 2 x VCC CL 30 pF 30 pF 50 pF 50 pF RL 1 kW 500 W 500 W 500 W VD 0.15 V 0.15 V 0.3 V 0.3 V http://onsemi.com 6 NL7SZ97 tW Input VM VM Timing Input VI 0V tsu Data Input VM VM th VM VI 0V VI 0V Figure 10. Voltage Waveforms Pulse Duration Input tPLH Output tPHL Output VM VM VM VM tPHL VM tPLH VM VI 0V VOH VOL VOH VOL Figure 11. Voltage Waveforms Setup and Hold Times Output Control Output Waveform 1 S1 at VLOAD (Note 8) tPZH Output Waveform 2 S1 at GND (Note 9) VM VM VM VI 0V VM VLOAD/2 VOL + VD VOL tPHZ VOH VOH − VD [0 V Figure 12. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs Figure 13. Voltage Waveforms Enable and Disable Times Low− and High−Level Enabling 8. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. 9. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 10. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. 11. The outputs are measured one at a time, with one transition per measurement. 12. All parameters are waveforms are not applicable to all devices. ORDERING INFORMATION Device NL7SZ97DFT2G Package SC−88 (Pb−Free) Shipping† 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NL7SZ97 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. DIM A A1 A3 b C D E e L HE M MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 D e 6 5 4 HE 1 2 3 −E− b 6 PL 0.2 (0.008) E M A3 C A SOLDERING FOOTPRINT* 0.50 0.0197 A1 L 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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