NLAS4053

NLAS4053 Analog Multiplexer/ Demultiplexer Triple 2:1 Analog Switch−Multiplexer Improved Process, Sub−Micron Silicon Gate CMOS The NLAS4053 is an improved version of the MC14053 and MC74HC4053 fabricated in sub−micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to ±3.0 V to pass a 6 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings. Pin for pin compatible with all industry standard versions of ‘4053.’ Features http://onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 1 NLAS4053G AWLYWW 16 TSSOP−16 DT SUFFIX CASE 948F 1 A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location) NLAS 4053 ALYWG G • Improved RDS(on) Specifications • Pin for Pin Replacement for MAX4053 and MAX4053A • − One Half the Resistance Operating at 5.0 Volts Single or Dual Supply Operation − Single 3−5 Volt Operation, or Dual ±3.0 Volt Operation − With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, − No Translators Needed − Address and Inhibit Pins are Over−Voltage Tolerant and May Be − Driven Up +6.0 V Regardless of VCC − Greatly Improved Noise Margin Over MAX4053 and MAX4053A Improved Linearity Over Standard HC4053 Devices • • Popular SOIC and the Space Saving TSSOP Packages • Pb−Free Packages are Available* ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 November, 2005 − Rev. 2 Publication Order Number: NLAS4053/D NLAS4053 NOB VCC 16 COMB COMC 15 14 NOC 13 NCC 12 AddC AddB 11 10 AddA 9 NCB NOA COMA NCA COMB COMC NOC NCC 1 NOB 2 NCB 3 NOA 4 5 6 7 VEE 8 GND Enable C B A COMA NCA Inhibit Figure 1. Pin Connection (Top View) Figure 2. Logic Diagram TRUTH TABLE Address Inhibit 1 0 C X don’t care 0 B X don’t care 0 A X don’t care 0 ON SWITCHES* All switches open COMA−NCA, COMB−NCB, COMC−NCC COMA−NOA, COMB−NCB, COMC−NCC COMA−NCA, COMB−NOB, COMC−NCC COMA−NOA, COMB−NOB, COMC−NCC COMA−NCA, COMB−NCB, COMC−NOC COMA−NOA, COMB−NCB, COMC−NOC COMA−NCA, COMB−NOB, COMC−NOC COMA−NOA, COMB−NOB, COMC−NOC 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 *NO, NC, and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction. http://onsemi.com 2 NLAS4053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎ Î Î ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol VEE Parameter Value Unit V V V V Negative DC Supply Voltage (Referenced to GND) −7.0 to )0.5 −0.5 to )7.0 −0.5 to )7.0 VCC VIS Positive DC Supply Voltage (Note 1) Analog Input Voltage Digital Input Voltage (Referenced to GND) (Referenced to VEE) VEE −0.5 to VCC )0.5 −0.5 to 7.0 $50 VIN I (Referenced to GND) DC Current, Into or Out of Any Pin Storage Temperature Range mA _C _C _C TSTG TL TJ −65 to )150 260 Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance )150 143 164 500 450 qJA PD SOIC TSSOP SOIC TSSOP °C/W mW Power Dissipation in Still Air, Moisture Sensitivity MSL FR Level 1 Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in u2000 u200 u1000 $300 VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) V ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 5) mA Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. The absolute value of VCC $ |VEE| ≤ 7.0. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î VEE Negative DC Supply Voltage Positive DC Supply Voltage Analog Input Voltage Digital Input Voltage (Referenced to GND) (Referenced to GND) (Referenced to VEE) −5.5 2.5 2.5 GND 5.5 6.6 V V V V VCC VIS VEE 0 VCC 5.5 VIN TA (Note 6) (Referenced to GND) Operating Temperature Range, All Package Types −55 0 0 125 100 20 _C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.0 V $ 0.3 V VCC = 5.0 V $ 0.5 V ns/V 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level. Symbol Parameter Min Max Unit http://onsemi.com 3 NLAS4053 ORDERING INFORMATION Device NLAS4053D NLAS4053DG NLAS4053DR2 NLAS4053DR2G NLAS4053DT NLAS4053DTG NLAS4053DTR2 NLAS4053DTR2G Package SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* TSSOP−16* TSSOP−16* Shipping† 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) VCC V 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 VIN = 6.0 or GND Channel Select, Enable and VIS = VCC or GND 0 V to 6.0 V 6.0 Guaranteed Limit −55 to 25°C 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 $0.1 4.0 v85°C 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 $1.0 40 v125°C 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 $1.0 80 Unit V Symbol VIH Parameter Minimum High−Level Input Voltage, Address and Inhibit Inputs Condition VIL Maximum Low−Level Input Voltage, Address and Inhibit Inputs V IIN ICC Maximum Input Leakage Current, Address or Inhibit Inputs Maximum Quiescent Supply Current (per Package) mA mA DC ELECTRICAL CHARACTERISTICS − Analog Section ÎÎ Î Î Î Î Î ÎÎ Î Î Î Î ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Î Î ÎÎ Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ ÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Î Symbol RON Parameter Test Conditions VCC V 3.0 4.5 3.0 3.0 4.5 3.0 VEE V Guaranteed Limit v85_C 108 46 33 20 18 15 4 2 −55 to 25°C 86 37 26 15 13 10 4 2 v125_C 120 55 37 20 18 15 5 3 Unit W Maximum “ON” Resistance VIN = VIL or VIH VIS = VEE to VCC |IS| = 10 mA (Figures 4 thru 9) VIN = VIL or VIH, |IS| = 10 mA, 0 0 −3.0 0 0 −3.0 DRON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VIS = 2.0 V VIS = 3.5 V VIS = 2.0 V W Rflat(ON) COM−NO On−Resistance Flatness Vcom 1, 2, 3.5 V Vcom −2, 0, 2 V |IS| = 10 mA 4.5 3.0 0 −3.0 0 −3.0 W INC(OFF) INO(OFF) Maximum Off−Channel Leakage Current Switch Off VIN = VIL or VIH VIO = VCC −1.0 V or VEE +1.0 V (Figure 17) Switch On VIO = VCC −1.0 V or VEE +1.0 V (Figure 17) 6.0 3.0 0.1 0.1 5.0 5.0 100 100 nA ICOM(ON) Maximum On−Channel Leakage Current, Channel− to−Channel 6.0 3.0 0 −3.0 0.1 0.1 5.0 5.0 100 100 nA http://onsemi.com 4 NLAS4053 AC CHARACTERISTICS (Input tr = tf = 3 ns) ÎÎ Î ÎÎÎÎÎÎ Î Î ÎÎ Î Î Î Î Î Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit Symbol tBBM Parameter Test Conditions VCC V 3.0 4.5 3.0 VEE V −55 to 25_C Min 1.0 1.0 1.0 Typ* 6.5 5.0 3.5 v85_C − − − v125_C − − − Unit ns Minimum Break−Before−Make Time VIN = VIL or VIH VIS = VCC RL = 300 W, CL = 35 pF (Figure 19) 0.0 0.0 −3.0 *Typical Characteristics are at 25_C. AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns) Guaranteed Limit VCC V 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 VEE V 0 0 0 −3.0 0 0 0 −3.0 0 0 0 −3.0 −55 to 25°C Min Typ Max 40 28 23 23 40 28 23 23 40 28 23 23 v85°C Min Max 45 30 25 25 45 30 25 25 45 30 25 25 Typical @ 25°C, VCC = 5.0 V CIN CNO or CNC CCOM C(ON) Maximum Input Capacitance,Select Inputs Analog I/O Common I/O Feedthrough 8 10 10 1.0 pF v125°C Min Max 50 35 30 28 50 35 30 28 50 35 30 28 Unit ns Symbol tTRANS Parameter Transition Time (Address Selection Time) (Figure 18) Turn−on Time (Figures 14, 15, 20, and 21) Enable to NO or NC Turn−off Time (Figures 14, 15, 20, and 21) Enable to NO or NC tON ns tOFF ns ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 5.0 3.0 VEE V 0.0 0.0 0.0 −3.0 0.0 0.0 0.0 −3.0 0.0 0.0 0.0 −3.0 0.0 −3.0 Typ 25°C 145 165 180 180 −93 −93 −93 −93 −2 −2 −2 −2 9.0 12 Unit MHz Symbol BW Parameter Maximum On−Channel Bandwidth or Minimum Frequency Response Off−Channel Feedthrough Isolation Condition VIS = ½ (VCC − VEE) Source Amplitude = 0 dBm (Figures 10 and 22) f = 100 kHz; VIS = ½ (VCC − VEE) Source = 0 dBm (Figures 12 and 22) VIS = ½ (VCC − VEE) Source = 0 dBm (Figures 10 and 22) VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 W, CL= 1000 pF, Q = CL * DVOUT (Figures 16 and 23) fIS = 1 MHz, RL = 10 KW, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 13) VISO dB VONL Maximum Feedthrough On Loss dB Q Charge Injection pC THD Total Harmonic Distortion THD + Noise % 6.0 3.0 0.0 −3.0 0.10 0.05 http://onsemi.com 5 NLAS4053 100 10 80 1 0.1 0.01 0.001 0.0001 0.00001 −40 VCC = 3.0 V 20 VCC = 5.0 V −20 0 20 60 80 100 120 0 −4.0 −2.0 0 2.0 VIS (VDC) 4.0 6.0 RON (W) ICC (nA) 60 2.0 V 100 40 $3.3 V 3.0 V 4.5 V 5.5 V Temperature (°C) Figure 3. ICC versus Temp, VCC = 3 V and 5 V 50 125°C 40 25°C RON (W) 30 Figure 4. RON versus VCC, Temp = 255C 100 90 80 70 RON (W) 60 50 40 30 20 10 0 −55°C 0.5 1.0 VCom (V) 1.5 2.0 85°C 125°C 85°C 25°C 20 10 0 0 0.5 1.0 −55°C 1.5 VCom (V) 2.0 2.5 3.0 Figure 5. Typical On Resistance VCC = 2.0 V, VEE = 0 V 25 85°C 25 85°C 20 15 Figure 6. Typical On Resistance VCC = 3.0 V, VEE = 0 V 125°C 125°C 20 RON (W) RON (W) 15 25°C 10 −55°C 5 10 25°C −55°C 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCom (V) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCom (V) Figure 7. Typical On Resistance VCC = 4.5 V, VEE = 0 V Figure 8. Typical On Resistance VCC = 5.5 V, VEE = 0 V http://onsemi.com 6 NLAS4053 25 125°C 20 85°C RON (W) 15 10 25°C −55°C 5 0 −4 −2 0 VCom (V) 2 4 Figure 9. Typical On Resistance VCC = 3.3 V, VEE = −3.3 V 50 40 30 PHASE SHIFT (Deg) BANDWIDTH (dB) 20 10 0 −10 −20 −30 −40 −50 0.1 1.0 10 100 FREQUENCY (mHz) BANDWIDTH (ON−RESPONSE) 90 72 54 36 18 0 −18 −36 −54 −72 −90 0.1 1.0 10 100 FREQUENCY (mHz) PHASE SHIFT Figure 10. Bandwidth Figure 11. Phase Shift 0 −10 OFF ISOLATION 10 dB/DIV −20 −30 −40 −50 −60 −70 −80 −90 −100 0.1 1.0 10 100 FREQUENCY (mHz) DISTORTION (%) 0 3.0 5.5 0.1 $3.3 4.5 0.01 10 100 1000 10000 10000 FREQUENCY (mHz) Figure 12. Off Isolation Figure 13. Total Harmonic Distortion http://onsemi.com 7 NLAS4053 30 TA = 25_C 25 20 15 10 5 0 2.5 tOFF (ns) tON (ns) TIME (ns) 25 20 15 10 5 0 −55 tON tOFF 30 VCC = 4.5 V TIME (ns) 3 3.5 4 4.5 5 −40 25 Temperature (°C) 85 125 VCC (VOLTS) Figure 14. tON and tOFF versus VCC Figure 15. tON and tOFF versus Temp 3.0 2.5 100 10 2.0 Q (pC) 1.5 1.0 0.5 0 −0.5 0 1 LEAKAGE (nA) VCC = 5 V 1 ICOM(ON) 0.1 VCC = 3 V 0.01 ICOM(OFF) VCC = 5.0 V INO(OFF) 0.001 2 VCOM (V) 3 4 5 −55 −20 25 70 85 125 TEMPERATURE (°C) Figure 16. Charge Injection versus COM Voltage Figure 17. Switch Leakage versus Temperature http://onsemi.com 8 NLAS4053 VCC 0.1 mF VEE Output VOUT 300 W 35 pF VCC Output Address Select Pin VEE 10% 90% VCC Input 0V 50% 50% ttrans ttrans Figure 18. Channel Selection Propagation Delay DUT VCC 0.1 mF 300 W Output VOUT 35 pF Input VCC GND tBMM 90% Output 90% of VOH Address Select Pin GND Figure 19. tBBM (Time Break−Before−Make) VCC DUT VCC 0.1 mF Open Output VOUT 300 W 35 pF Output GND tON tOFF Input 0V VOH 90% 90% 50% 50% Input Enable Figure 20. tON/tOFF http://onsemi.com 9 NLAS4053 VCC DUT Output Open 300 W VOUT 35 pF Input VCC 50% 0V VCC Output VOL tOFF 10% tON 10% 50% Input Enable Figure 21. tON/tOFF 50 W Reference Input Output 50 W Generator 50 W DUT Transmitted Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz VOUT for VIN at 100 kHz to 50 MHz VIN Bandwidth (BW) = the frequency 3 dB below VONL Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL http://onsemi.com 10 NLAS4053 DUT Open Output VIN VCC GND CL Output Off Off DVOUT VIN On Figure 23. Charge Injection: (Q) TYPICAL OPERATION +5.0 V 16 VCC 16 +3.0 V VCC VEE GND 7 8 VEE GND −3.0 V 7 8 Figure 24. 5.0 Volts Single Supply VCC = 5.0 V, VEE = 0 Figure 25. Dual Supply VCC = 3.0 V, VEE = −3.0 V http://onsemi.com 11 NLAS4053 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 −B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 12 NLAS4053 PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE A 16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K 16 2X L/2 9 J1 B −U− L PIN 1 IDENT. 1 8 J N 0.15 (0.006) T U S 0.25 (0.010) M A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE H D G DETAIL E http://onsemi.com 13 ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ ÇÇÇ K1 SECTION N−N −W− DIM A B C D F G H J J1 K K1 L M NLAS4053 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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