NLAS4157DFT2G

NLAS4157 Analog Switch, SPDT, 1 W RON The NLAS4157 is a low RON SPDT analog switch. This device is designed for low operating voltage, high current switching of speaker output for cell phone applications. It can switch a balanced stereo output. The NLAS4157 can handle a balanced microphone/speaker/ringtone generator in a monophone mode. The device contains a break−before−make (BBM) feature. http://onsemi.com 1 Features SC−88 (SOT−363) CASE 419B • Single Supply Operation: • • • • 1.65 V to 5.5 V VCC Function Directly from LiON Battery Tiny SC88 6−Pin Pb−Free Package: Meets JEDEC MO−220 Specifications RON Typical = 0.8  @ VCC = 4.5 V Low Static Power This is a Pb−Free Device MARKING DIAGRAM 6 AN MG G 1 AN = Specific Device Code M = Date Code* G = Pb−Free Package Typical Applications • Cell Phone Speaker/Microphone Switching • Ringtone−Chip/Amplifier Switching • Stereo Balanced (Push−Pull) Switching (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. Important Information • • • • Ringtone−Chip/Amplifier Switching Continuous Current Rating Through each Switch ±300 mA Conforms to: JEDEC MO−220, Issue H, Variation VEED−6 Pin for Pin Compatible with FSA4157 PIN ASSIGNMENTS B1 1 6 S GND 2 5 VCC B0 3 4 A (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 3 1 Publication Order Number: NLAS4157/D NLAS4157 A B0 B1 S Figure 1. Input Equivalent Circuit PIN DESCRIPTION Pin Name TRUTH TABLE Description Control Input Function A, B0, B1 Data Ports L B0 Connected to A S Control Input H B1 Connected to A H = HIGH Logic Level. L = LOW Logic Level. MAXIMUM RATINGS Symbol Rating Value Unit −0.5 to +6.0 V −0.5 to VCC +0.5 V −0.5 to +6.0 V Continuous DC Current from COM to NC/NO ±300 mA Ianl−pk1 Peak Current from COM to NC/NO, 10 Duty Cycles (Note 1) ±500 mA Iclmp Continuous DC Current into COM/NC/NO with respect to VCC or GND ±100 mA VCC Positive DC Supply Voltage VIS Analog Input Voltage (VNO, VNC, or VCOM) VIN Digital Select Input Voltage Ianl1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Defined as 10% ON, 90% off duty cycle. RECOMMENDED OPERATING CONDITIONS Symbol Rating Min Max Unit 1.65 5.5 V VCC Positive DC Supply Voltage VIS Analog Input Voltage (A, B0, B1) 0 VCC V VIN Digital Select Input Voltage (S) 0 VCC V TA Operating Temperature Range −40 85 °C tr, tf Input Rise or Fall Time, SELECT 20 10 ns/V VCC = 3.0 V VCC = 5.5 V http://onsemi.com 2 NLAS4157 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC (V) Test Conditions TA = +25°C Min Typ VIH HIGH Level Input Voltage 2.7 4.5 VIL LOW Level Input Voltage 2.7 4.5 IIN Input Leakage Current 0 v VIN v 5.5 V 0−5.5 IOFF OFF State Leakage Current (Note 7) 0 v A, B v VCC 5.5 ION ON State Leakage Current (Note 7) 0 v A, B v VCC 5.5 RON Switch On Resistance (Note 2) IO = −100 mA, B0 or B1 = 3.5 V 2.7 IO = −100 mA, B0 or B1 = 1.5 V 4.5 VIN = VCC or GND, IOUT = 0 5.5 On Resistance Match Between Channels (Notes 2, 3, 4) IA = −100 mA, B0 or B1 = 1.5 V IA = −100 mA, B0 or B1 = 3.5 V 2.7 0.15 4.5 0.12 On Resistance Flatness (Notes 2, 3, 5) IA = −100 mA, B0 or B1 = 0 V, 0.75 V, 1.5 V IA = −100 mA, B0 or B1 = 0 V, 1.0 V, 2.0 V 2.7 1.4 4.5 0.3 ICC Quiescent Supply Current All Channels ON or OFF TA = −40°C to +85°C Max Min Max 2.0 2.4 Unit V 0.6 0.8 V ±0.1 ±1 A −2.0 +2.0 ±20 nA −4.0 +4.0 ±40 nA 2.0 4.0 4.3  0.8 1.15 1.3 0.5 1.0 A Analog Signal Range RON Rflat  0.15  0.4 2. Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B Ports). 3. Parameter is characterized but not tested in production. 4. DRON = RON max − RON min measured at identical VCC, temperature and voltage levels. 5. Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions. 6. Guaranteed by Design. 7. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). http://onsemi.com 3 NLAS4157 AC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VCC (V) TA = +25°C Min Typ TA = −40°C to +85°C Max Min Max tPHL tPLH Propagation Delay Bus−to−Bus (Note 9) VI = OPEN 2.7 4.5 2.0 0.3 tON Output Enable Time Turn On Time (A to Bn) B0 or B1 = 1.5 V, RL = 50 , CL = 35 pF B0 or B1 = 3.0 V, RL = 50 , CL = 35 pF 2.7 30 35 4.5 20 25 Output Disable Time Turn Off Time (A Port to B Port) B0 or B1 = 1.5V, RL = 50 , CL = 35 pF B0 or B1 = 3.0 V, RL = 50 , CL = 35 pF 2.7 20 25 4.5 15 20 tOFF tBBM Break Before Make Time (Note 8) Q Charge Injection (Note 8) CL = 1.0 nF, VGEN = 0 V RGEN = 0  OIRR Off Isolation (Note 10) Xtalk 2.7 0.5 0.5 4.5 0.5 0.5 Unit Figure # ns 3, 4 ns 3, 4 ns 3, 4 ns 2 2.7 4.5 26 48 pC 6 RL = 50  f = 1.0 MHz 2.7 − 5.5 −52 dB 5 Crosstalk RL = 50  f = 1.0 MHz 2.7 − 5.5 −57 dB 7 BW −3 dB Bandwidth RL = 50  2.7 − 5.5 40 MHz 8 THD Total Harmonic Distortion (Note 8) RL = 600  0.5 VP−P f = 20 Hz to 20 kHz 2.7 − 5.5 0.012 % 9 8. Guaranteed by Design. 9. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). 10. Off Isolation = 20 log10 [VA/VBn]. CAPACITANCE (Note 11) Symbol Parameter Test Conditions Typ Max Unit CIN Select Pin Input Capacitance VCC = 0 V, f = 1 MHz 10 pF CIO−B B Port Off Capacitance VCC = 4.5 V, f = 1 MHz 25 pF CIOA−ON A Port Capacitance when Switch is Enabled VCC = 4.5 V, f = 1 MHz 87 pF Figure # 11. TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested in production. DEVICE ORDERING INFORMATION Device Order Number NLAS4157DFT2G Package Shipping† SC−88 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NLAS4157 VCC DUT VCC Input Output GND VOUT 0.1 F 50  tBMM 35 pF 90% 90% of VOH Output Switch Select Pin GND Figure 2. tBBM (Time Break−Before−Make) VCC Input DUT VCC 0.1 F 50% Output VOUT Open 50% 0V 50  VOH 90% 35 pF 90% Output VOL Input tON tOFF Figure 3. tON/tOFF VCC VCC Input DUT Output 50% 0V 50  VOUT Open 50% VOH 35 pF Output Input tOFF Figure 4. tON/tOFF http://onsemi.com 5 10% 10% VOL tON NLAS4157 50  DUT Reference Transmitted Input Output 50  Generator 50  Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. ǒVVOUT Ǔ for VIN at 100 kHz IN VOUT Ǔ for VIN at 100 kHz to 50 MHz VONL = On Channel Loss = 20 Log ǒ VIN VISO = Off Channel Isolation = 20 Log Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50  Figure 5. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL DUT VCC VIN Output Open GND CL Output Off VIN Figure 6. Charge Injection: (Q) http://onsemi.com 6 On Off VOUT NLAS4157 0 0 −10 −2 −20 −4 BW (dB) XT (dB) −30 −40 −50 −6 −8 −60 −10 −70 −80 0.1 1.0 10 100 −12 0.1 1000 1.0 100 10 FREQUENCY (MHz) 1000 FREQUENCY (MHz) Figure 7. Cross Talk vs. Frequency @ VCC = 4.5 V Figure 8. Bandwidth vs. Frequency 0.005 2.5 0.0045 0.004 2 0.003 RON () THD (%) 0.0035 0.0025 0.002 1.5 25°C 85°C −40°C 1 0.0015 0.001 0.5 0.0005 0 10 100 1000 10000 100000 0.5 1.0 1.5 2.0 3.0 2.5 FREQUENCY (Hz) VIS (V) Figure 9. Total Harmonic Distortion Figure 10. On−Resistance vs. Signal Voltage @ VCC = 2.7 V 1 2.5 0.9 85°C 0.8 0.7 2.7 V 2.0 25°C 0.6 RON () RON () 0 0.0 −40°C 0.5 0.4 1.5 3.0 V 3.6 V 1.0 0.3 0.2 4.5 V 0.5 0.1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.0 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIS (V) VIS (V) Figure 11. On−Resistance vs. Signal Voltage @ VCC = 4.5 V Figure 12. On−Resistance vs. Signal Voltage http://onsemi.com 7 5.0 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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