NLAS44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS44599 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAS44599 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
16
16
1
QFN−16
MN SUFFIX
CASE 485G
1
AS
4459
ALYW
Current
Part Marking
C
ALYW
Previous
Part Marking*
*Previous releases of this device may be marked as
shown in this diagram.
Channel Select Input Over−Voltage Tolerant to 5.5 V
16
Fast Switching and Propagation Speeds
NLAS
4459
ALYW
16
Break−Before−Make Circuitry
1
Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latch−up Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 158 FETs
TSSOP−16
DT SUFFIX
CASE 948F
A
L
Y
W
•
• Pb−Free Packages are Available
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 14
1
Publication Order Number:
NLAS44599/D
NLAS44599
QFN−16 PACKAGE
0
NO A0
1
NC A1
2
NO B0
2/3
3
NC B1
X1
0
NO C0
1
NC C1
2
U
NO D0
3
U
U
COM A
NO A0
VCC
NC D1
1
2
3
NC B1
GND
NO C0
COM C
4
COM A
X1
U
5
6
7
8
SELECT AB
U
NC C1
NC to COM
NO to COM
U
SCD
L
H
U
NO D0
On Channel
U
See TSSOP−16
Switch Configuration
COM D
Select AB or CD
U
13
9
COM B
14
10
NO B0
15
11
SAB
16
12
NC A1
FUNCTION TABLE
NC D1
0/1
TSSOP−16 PACKAGE
16
VCC
SELECT CD
COM C
COM A
2
15
NC D1
NC A1
3
14
COM D
SELECT AB
4
13
NO D0
NO B0
5
12
SELECT CD
COM B
6
11
NC C1
NC B1
7
10
COM C
GND
8
9
NO C0
Figure 1. Logic Diagram
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2
COM D
U
1
U
NO A0
U
COM B
0/1
2/3
Figure 2. IEC Logic Symbol
NLAS44599
MAXIMUM RATINGS
Symbol
Parameter
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage (VNO or VCOM)
VIN
Digital Select Input Voltage
IIK
DC Current, Into or Out of Any Pin
PD
Power Dissipation in Still Air
TSTG
Storage Temperature Range
TL
Value
Unit
*0.5 to )7.0
V
*0.5 v VIS v VCC )0.5
*0.5 v VI v)7.0
V
$50
mA
800
450
mW
*65 to )150
°C
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
2000
200
1000
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 125°C (Note 4)
$300
mA
JA
Thermal Resistance
80
164
°C/W
QFN−16
TSSOP−16
Level 1
Oxygen Index: 30% − 35%
UL 94−V0 (0.125 in)
QFN−16
TSSOP−16
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
VIN
Digital Select Input Voltage
GND
5.5
V
VIS
Analog Input Voltage (NC, NO, COM)
GND
VCC
V
TA
Operating Temperature Range
*55
)125
°C
tr, tf
Input Rise or Fall Time, SELECT
0
0
100
20
ns/V
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80°C
117.8
TJ = 90°C
1,032,200
TJ = 100°C
80
TJ = 110°C
Time, Years
TJ = 120°C
Time, Hours
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130°C
Junction
Temperature 5C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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3
NLAS44599
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Condition
VCC
*555C to 255C
t855C
t1255C
Unit
VIH
Minimum High−Level Input
Voltage, Select Inputs
2.0
2.5
3.0
4.5
5.5
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
V
VIL
Maximum Low−Level Input
Voltage, Select Inputs
2.0
2.5
3.0
4.5
5.5
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
V
IIN
Maximum Input Leakage
Current
VIN = 5.5 V or GND
5.5
$0.2
$2.0
$2.0
A
IOFF
Power Off Leakage Current,
Select Inputs
VIN = 5.5 V or GND
0
$10
$10
$10
A
ICC
Maximum Quiescent Supply
Current
Select and VIS = VCC or GND
5.5
4.0
4.0
8.0
A
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
Symbol
Parameter
Condition
VCC
*555C to 255C
t855C
t1255C
Unit
RON
Maximum “ON” Resistance
(Figures 17 − 23)
VIN = VIL or VIH
VIS = GND to VCC
IINI v 10.0 mA
2.5
3.0
4.5
5.5
85
45
30
25
95
50
35
30
105
55
40
35
RFLAT (ON)
ON Resistance Flatness
(Figures 17 − 23)
VIN = VIL or VIH
IINI v 10.0 mA
VIS = 1 V, 2 V, 3.5 V
4.5
4
4
5
INC(OFF)
INO(OFF)
NO or NC Off Leakage
Current (Figure 9)
VIN = VIL or VIH
VNO or VNC = 1.0 VCOM 4.5 V
5.5
1
10
100
nA
ICOM(ON)
COM ON Leakage Current
(Figure 9)
VIN = VIL or VIH
VNO 1.0 V or 4.5 V with VNC floating or
VNO 1.0 V or 4.5 V with VNO floating
VCOM = 1.0 V or 4.5 V
5.5
1
10
100
nA
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4
NLAS44599
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Maximum Limit
Parameter
Symbol
Test Conditions
*555C to 255C
t855C
t1255C
VCC
(V)
VIS
(V)
Min
Typ*
Max
Min
Max
Min
Max
Unit
tON
Turn−On Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
5
5
2
2
23
16
11
9
35
24
16
14
5
5
2
2
38
27
19
17
5
5
2
2
41
30
22
20
ns
tOFF
Turn−Off Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
7
5
4
3
12
10
6
5
1
1
1
1
15
13
9
8
1
1
1
1
18
16
12
11
ns
tBBM
Minimum Break−Before−Make
Time
VIS = 3.0 V (Figure 4)
RL = 300 CL = 35 pF
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
12
11
6
5
1
1
1
1
1
1
1
1
ns
Typical @ 25, VCC = 5.0 V
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
pF
8
10
10
20
*Typical Characteristics are at 25°C.
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
Condition
VCC
V
Typical
255C
Unit
BW
Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response (Figure 11)
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
145
170
175
MHz
VONL
Maximum Feedthrough On Loss
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−3
−3
−3
dB
VISO
Off−Channel Isolation (Figure 10)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−93
−93
−93
dB
Q
Charge Injection Select Input to
Common I/O (Figure 15)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 , CL = 1000 pF
Q = CL * VOUT
(Figure 8)
3.0
5.5
1.5
3.0
Total Harmonic Distortion THD +
Noise (Figure 14)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 , CL = 50 pF
VIS = 5.0 VPP sine wave
5.5
0.1
Channel−to−Channel Crosstalk
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
5.5
3.0
−90
−90
THD
VCT
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5
pC
%
dB
NLAS44599
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300
tBMM
35 pF
90%
90% of VOH
Output
Switch Select Pin
GND
Figure 4. tBBM (Time Break−Before−Make)
VCC
Input
DUT
VCC
0.1 F
50%
Output
VOUT
Open
50%
0V
300
VOH
90%
35 pF
90%
Output
VOL
Input
tON
tOFF
Figure 5. tON/tOFF
VCC
VCC
Input
DUT
Output
50%
VOUT
Open
50%
0V
300
VOH
35 pF
Output
10%
VOL
Input
tOFF
Figure 6. tON/tOFF
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6
10%
tON
NLAS44599
50
DUT
Reference
Transmitted
Input
Output
50 Generator
50
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
VOUT
Ǔ for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log ǒ
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
On
VIN
Figure 8. Charge Injection: (Q)
100
LEAKAGE (nA)
10
1
0.1
ICOM(ON)
ICOM(OFF)
0.01
0.001
−55
VCC = 5.0 V
INO(OFF)
−20
25
70
85
TEMPERATURE (°C)
Figure 9. Switch Leakage vs. Temperature
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7
125
Off
VOUT
NLAS44599
+15
0
1.0
2.0
−20
+10
Bandwidth
(ON−RESPONSE)
+5
3.0
−40
4.0
(dB)
(dB)
Off Isolation
−60
VCC = 5.0 V
TA = 25°C
−80
−100
0.01
0.1
−10
6.0
−15
7.0
−20
8.0
9.0
10.0
0.01
100 200
1
10
FREQUENCY (MHz)
25
20
20
TIME (ns)
TIME (ns)
25
15
tON (ns)
tOFF (ns)
0
2.5
3
3.5
4
−30
0.1
1
−35
100 300
10
Figure 11. Typical Bandwidth and Phase Shift
30
5
−25
VCC = 5.0 V
TA = 25°C
FREQUENCY (MHz)
30
10
−5
5.0
Figure 10. Off−Channel Isolation
4.5
VCC = 4.5 V
15
10
tON
5
tOFF
0
−55
5
−40
25
85
125
VCC (VOLTS)
Temperature (°C)
Figure 12. tON and tOFF vs. VCC at 25°C
Figure 13. tON and tOFF vs. Temp
1
3.0
VINpp = 3.0 V
VCC = 3.6 V
2.5
2.0
Q (pC)
THD + NOISE (%)
0
PHASE SHIFT
PHASE (°)
0
0.1
VINpp = 5.0 V
VCC = 5.5 V
VCC = 5 V
1.5
1.0
0.5
VCC = 3 V
0
0.01
1
10
−0.5
0
100
1
2
3
4
FREQUENCY (kHz)
VCOM (V)
Figure 14. Total Harmonic Distortion
Plus Noise vs. Frequency
Figure 15. Charge Injection vs. COM Voltage
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8
5
NLAS44599
100
100
VCC = 2.0 V
10
80
RON ()
1
ICC (nA)
0.1
0.01
60
VCC = 2.5 V
40
VCC = 3.0 V
0.001
VCC = 3.0 V
VCC = 4.0 V
20
0.0001
VCC = 5.0 V
0.00001
−40
−20
0
20
60
VCC = 5.5 V
80
100
0
0.0
120
80
70
70
60
60
RON ()
90
50
40
125°C
30
40
10
85°C
0.5
25°C
20
−55°C
1.0
1.5
2.0
0
0.0
2.5
−55°C
85°C
125°C
0.5
1.0
1.5
VIS (VDC)
2.0
2.5
3.0
VIS (VDC)
Figure 18. RON vs Temp, VCC = 2.0 V
Figure 19. RON vs. Temp, VCC = 2.5 V
30
50
45
25
40
35
20
30
RON ()
RON ()
6.0
50
30
25°C
20
25
20
125°C
15
15
10
85°C
10
0
0.0
5.0
Figure 17. RON vs. VCC, Temp = 255C
80
5
4.0
Figure 16. ICC vs. Temp, VCC = 3 V & 5 V
90
RON ()
3.0
VIS (VDC)
100
0
0.0
2.0
Temperature (°C)
100
10
1.0
−55°C
0.5
5
25°C
1.0
1.5
2.0
2.5
3.0
3.5
0
0.0
25°C
85°C
125°C
−55°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIS (VDC)
VIS (VDC)
Figure 21. RON vs. Temp, VCC = 4.5 V
Figure 20. RON vs. Temp, VCC = 3.0 V
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9
4.5
NLAS44599
25
25
125°C
20
20
RON ()
RON ()
125°C
15
25°C
10
−55°C
85°C
5
15
25°C
10
85°C
−55°C
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
5.0
VIS (VDC)
VIS (VDC)
Figure 22. RON vs. Temp, VCC = 5.0 V
Figure 23. RON vs. Temp, VCC = 5.5 V
DEVICE ORDERING INFORMATION
Device Nomenclature
Circuit
Indicator
Technology
Device
Function
Package
Suffix
NLAS44599DT
NL
AS
44599
DT
NLAS44599DTR2
NL
AS
44599
DT
NLAS44599MN
NL
AS
44599
NLAS44599MNG
NL
AS
NLAS44599MNR2
NL
NLAS44599MNR2G
NL
Device
Tape & Reel
Suffix
Package Type
Shipping†
TSSOP−16*
96 / Unit Rail
TSSOP−16*
2500 / Tape & Reel
MN
QFN−16
124 Unit / Rail
44599
MN
QFN−16
(Pb−Free)
124 Unit / Rail
AS
44599
MN
R2
QFN−16
2500 / Tape & Reel
AS
44599
MN
R2
QFN−16
(Pb−Free)
2500 / Tape & Reel
R2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE G
1
SCALE 2:1
DATE 08 OCT 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04795D
QFN16 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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