NLAS7222B, NLAS7222C High-Speed USB 2.0 (480 Mbps) DPDT Switches
ON Semiconductor's NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company's advanced sub-micron CMOS technology, achieving industry-leading performance. Both the NLAS7222B and NLAS7222C are 2- to 1-port analog switches. Their wide bandwidth and low bit-to-bit skew allow them to pass high-speed differential signals with good signal integrity. Each switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. Industry-leading advantages include a propagation delay of less than 250 ps, resulting from its low channel resistance and low I/O capacitance. Their high channel-to-channel crosstalk rejection results in minimal noise interference. Their bandwidth is wide enough to pass High-Speed USB 2.0 differential signals (480 Mb/s).
Features http://onsemi.com MARKING DIAGRAM
UQFN-10 CASE 488AT 1 XX =
XX M G G
• • • • • • • • •
RON is Typically 8.0 W at VCC = 3.3 V Low Bit-to-Bit Skew: Typically 50 ps Low Crosstalk: -30 dB @ 250 MHz Low Current Consumption: 1.0 mA Near-Zero Propagation Delay: 250 ps Channel On-Capacitance: 8.0 pF (Typical) VCC Operating Range: 1.65 V to 4.5 V > 700 MHz Bandwidth (or Data Frequency) These are Pb-Free Devices
Device Code xx = 2A or Y M = Date Code G = Pb-Free Device (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
Typical Applications
• Differential Signal Data Routing • USB 2.0 Signal Routing
Important Information
• Continuous Current Rating Through Each Switch ±50 mA • 8 kV I/O to GND ESD Protection
© Semiconductor Components Industries, LLC, 2007
1
August, 2007 - Rev. 1
Publication Order Number: NLAS7222B/D
NLAS7222B, NLAS7222C
HSD17
HSD26
HSD1+
7
HSD16
OE VCC
8
5
DGND
OE VCC
8
5
HSD2+ HSD2-
9
CONTROL
4
9
4
CONTROL S
10 3
D+
S
10
3
GND
1
2
1
2
HSD1+
HSD2+
D+
D-
Figure 1. Pin Connections and Logic Diagram (NLAS7222B, Top View) Table 1. PIN DESCRIPTION
Pin S OE HSD1+, HSD1-, HSD2+, HSD2-, D+, DFunction Select Input Output Enable Data Ports
Figure 2. Pin Connections and Logic Diagram (NLAS7222C, Top View) Table 2. TRUTH TABLE
OE 1 0 0 S X 0 1 HSD1+, HSD1OFF ON OFF HSD2+, HSD2OFF OFF ON
MAXIMUM RATINGS
Symbol VCC VIS Pins VCC HSD1+, HSD1HSD2+, HSD2D+, DVIN ICC TS IIS_CON HSD1+, HSD1HSD2+, HSD2-, D+, DHSD1+, HSD1HSD2+, HSD2-, D+, DOE OE VCC Control Input Voltage Positive DC Supply Current Storage Temperature Analog Signal Continuous Current-Closed Switch Parameter Positive DC Supply Voltage Analog Signal Voltage Value -0.5 to +5.5 -0.5 to VCC + 0.3 -0.5 to +5.5 -0.5 to +5.5 50 -65 to +150 $300 V mA °C mA Unit V V
IIS_PK
Analog Signal Continuous Current 10% Duty Cycle
$500
mA
IIN
Control Input Current
$20
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIS HSD1+, HSD1HSD2+, HSD2D+, DVIN TA OE Digital Select Input Voltage Operating Temperature Range Pins Parameter Positive DC Supply Voltage Analog Signal Voltage Min 1.65 GND GND GND - 40 Max 4.5 VCC 4.5 VCC +85 V °C Unit V V
Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable. Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable. These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions.
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NLAS7222B, NLAS7222C
ESD PROTECTION
Symbol ESD ESD Human Body Model - All Pins Human Body Model - I/O to GND Parameter Value 2.0 8.0 Unit kV kV
DC ELECTRICAL CHARACTERISTICS
CONTROL INPUT (Typical: T = 25°C, VCC = 3.3 V)
- 40°C to +85°C Symbol VIH Pins OE Parameter Control Input HIGH Voltage (See Figure 3) Control Input LOW Voltage (See Figure 3) Control Input Leakage Current 0 ≤ VIS ≤ VCC Test Conditions VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 1.65 - 4.5 Min 1.3 1.4 1.6 Typ Max Unit V
VIL
OE
0.4 0.4 0.5 ±1.0
V
IIN
OE
-
mA
SUPPLY AND LEAKAGE CURRENT (Typical: T = 25°C, VCC = 3.3 V)
- 40°C to +85°C Symbol ICC ICCT Pins VCC VCC Parameter Quiescent Supply Current Increase in ICC per Control Voltage OFF State Leakage Current Power OFF Leakage Current Test Conditions VIS = VCC or GND; IOUT = 0A VIN = 2.6 V VCC (V) 1.65 - 4.5 3.6 Min Typ Max 1.0 10 Unit mA mA
IOZ IOFF
HSD1+, HSD1HSD2+, HSD2D+, D-
0 ≤ VIS ≤ VCC 0 ≤ VIS ≤ 4.5 V
1.65 - 4.5 0
-
-
±1.0 ±1.0
mA mA
HIGH SPEED ON RESISTANCE (Typical: T = 25°C, VCC = 3.3 V)
- 40°C to +85°C Symbol RON Pins Parameter On-Resistance Test Conditions VIS = 0 V to 0.4 V, ION = 8 mA VIS = 0 V to 1.0 V, ION = 8 mA VIS = 0 V to 0.4 V, ION = 8 mA VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 2.7 3.3 4.2 Min Typ 9.0 8.0 7.0 1.6 1.5 1.4 1.05 0.85 0.65 Max 12 10 8.0 Unit W
RFLAT
On-Resistance Flatness On-Resistance Matching
-
W
DRON
-
-
W
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NLAS7222B, NLAS7222C
DC ELECTRICAL CHARACTERISTICS (continued)
FULL SPEED ON RESISTANCE (Typical: T = 25°C, VCC = 3.3 V)
- 40°C to +85°C Symbol RON Pins Parameter On-Resistance Test Conditions VIS = 0 V to VCC, ION = 8 mA VIS = 0 V to 1.0 V, ION = 8 mA VIS = 0 V to VCC, ION = 8 mA VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 2.7 3.3 4.2 Min Typ 9.0 8.5 7.5 1.6 1.5 1.4 2.20 2.45 2.65 Max 12 10.5 8.5 Unit W
RFLAT
On-Resistance Flatness On-Resistance Matching
W
DRON
W
AC ELECTRICAL CHARACTERISTICS
TIMING/FREQUENCY (Typical: T = 25°C, VCC = 3.3 V, RL = 50 W, CL = 5 pF, f = 1 MHz)
-40 5C to +855C Symbol tON tOFF tBBM BW Pins Parameter Test Conditions VCC (V) 1.65 - 4.5 1.65 - 4.5 1.65 - 4.5 CL = 5 pF CL = 0 pF 1.65 - 4.5 Min 3.0 Typ 14 10 4.4 500 750 Max 30 20 7.0 Unit ns ns ns MHz Closed Turn-ON Time to Open Open to Turn-OFF Time Closed Break-Before-Make Delay -3 dB Bandwidth
ISOLATION (Typical: T = 25°C, VCC = 3.3 V, RL = 50 W, CL = 5 pF, f = 1 MHz)
-40 5C to +855C Symbol OIRR XTALK Pins Open HSD1+ to HSD1Parameter OFF-Isolation Non-Adjacent Channel Crosstalk Test Conditions f = 250 MHz f = 250 MHz VCC (V) 1.65 - 4.5 1.65 - 4.5 Min Typ -22 -30 Max Unit dB dB
NLAS7222B CAPACITANCE (Typical: T = 25°C, VCC = 3.3 V, RL = 50 W, CL = 5 pF, f = 1 MHz)
-40 5C to +855C Symbol CIN CON Pins OE D+ to HSD1+ or HSD2+ HSD2+, HSD2Parameter Control Pin Input Capacitance ON Capacitance Test Conditions VCC = 0 V VCC = 3.3 V; OE = 0 V Min Typ 3.0 8.0 Max Unit pF pF
COFF
OFF Capacitance
VCC = VIS = 3.3 V; OE = 3.3 V
-
4.5
-
pF
NLAS7222C CAPACITANCE (Typical: T = 25°C, VCC = 3.3 V, RL = 50 W, CL = 5 pF, f = 1 MHz)
-40 5C to +855C Symbol CIN CON Pins OE D+ to HSD1+ or HSD2+ HSD2+, HSD2Parameter Control Pin Input Capacitance ON Capacitance Test Conditions VCC = 0 V VCC = 3.3 V; OE = 0 V Min Typ 3.0 10 Max Unit pF pF
COFF
OFF Capacitance
VCC = VIS = 3.3 V; OE = 3.3 V
-
5.5
-
pF
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NLAS7222B, NLAS7222C
140 120 100 ICC, (mA) 80 60 40 VCC = 2.7 V 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VIN, (V) VCC = 4.2 V VCC = 3.3 V
Figure 3. ICC vs. VIN
DUT VCC 0.1 mF 50 W Output VOUT 35 pF Input
VCC GND
tBMM Output 50 % OF DROOP Switch Select Pin VOLTAGE DROOP
Figure 4. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 50 W 35 pF Output VOL Input tON tOFF Input 0V VOH 90% 90% 50% 50%
Figure 5. tON/tOFF
VCC DUT Output Open 50 W VOUT 35 pF Output VOL Input tOFF 10% 10% Input 0V VOH VCC 50% 50%
tON
Figure 6. tON/tOFF
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NLAS7222B, NLAS7222C
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz
VOUT for VIN at 100 kHz to 50 MHz VIN
Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 W
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
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NLAS7222B, NLAS7222C
APPLICATIONS INFORMATION The low on resistance and capacitance of the NLAS7222B provides for a high bandwidth analog switch suitable for applications such as USB data switching. Results for the USB 2.0 signal quality tests will be shown in this section, along with a description of the evaluation test board. The data for the eye diagram signal quality and jitter tests verifies that the NLAS7222B can be used as a data switch in low, full and high speed USB 2.0 systems. Figures 8, 9 and 10 provide a description of the test evaluation board. The USB tests were conducted per the procedures provided by the USB Implementers Forum (www.usb.org), the industry group responsible for defining the USB certification requirements. The test patterns were generated by a PC and MATLAB software, and were inputted to the analog switch through USB connectors J1 (HSD1) or J2 (HSD2). A USB certified device was plugged into connector J4 to function as a data transceiver. The high speed and full speed tests used a flash memory device, while the low speed tests used a mouse. Test connectors J3 and J5 provide a direct connection of the USB device and were used to verify that the analog switch does not distort the data signals.
Figure 8. Schematic of the NLAS7222B USB Demo Board
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NLAS7222B, NLAS7222C
Figure 9. Block Diagram of the NLAS7222B USB Demo Board
Figure 10. Photograph of the NLAS7222B USB Demo Board
ORDERING INFORMATION
Device NLAS7222BMUTBG Package UQFN-10 (Pb-Free) Shipping† 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NLAS7222B, NLAS7222C
PACKAGE DIMENSIONS
10 PIN UQFN, 1.4x1.8, 0.4P CASE 488AT-01 ISSUE O
D A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 b D E e L L3 MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.40 0.60
PIN 1 REFERENCE 2X
0.10 C 0.10 C
2X
0.05 C 0.05 C
10X
9XL 6
L3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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ÉÉÉ ÉÉÉ ÉÉÉ
A A1
3 5 1 10 10 X
E
B
C
SEATING PLANE
MOUNTING FOOTPRINT*
1.700 0.0669
9X
e/2
0.663 0.0261 0.200 0.0079
1
0.563 0.0221
e
b
0.10 C A B 0.05 C
NOTE 3
2.100 0.0827 0.400 0.0157 PITCH
10 X
0.225 0.0089
SCALE 20:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLAS7222B/D