NLAST4053
Analog Multiplexer/
Demultiplexer
TTL Compatible, Triple 2:1 Analog
Switch–Multiplexer Improved Process,
Sub–Micron Silicon Gate CMOS
The NLAST4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub–micron Silicon Gate CMOS
technology for lower RDS(on) resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to ±3 V to pass a 6 VPP signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
VEE, pin 7 to ground. For dual supply operation, VEE is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit pins are standard TTL
level compatible. For CMOS compatibility see NLAS4053. Pin for
pin compatible with all industry standard versions of ‘4053.’
• Improved RDS(on) Specifications
• Pin for Pin Replacement for MAX4053 and MAX4053A
•
•
– One Half the Resistance Operating at 5.0 Volts
Single or Dual Supply Operation
– Single 3–5 Volt Operation, or Dual ±3 Volt Operation
– With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
– No Translators Needed
– Address and Inhibit Pins are Over–Voltage Tolerant and May Be
– Driven Up +6 V Regardless of VCC
Address and Inhibit Pins are Standard TTL Compatible
– Greatly Improved Noise Margin Over MAX4053 and MAX4053A
– True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V
Improved Linearity Over Standard HC4053 Devices
•
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
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MARKING DIAGRAMS
16
SO–16
D SUFFIX
CASE 751B
8
16
9
NLAST
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
QSOP–16
QS SUFFIX
CASE 492
A
L, WL
Y
W
Device
June, 2002 – Rev. 0
1
1
8
16
9
NLAST
4053
ALYW
1
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Packages
Semiconductor Components Industries, LLC, 2002
9
NLAST4053
AWLYWW
1
Package
Shipping
NLAST4053D
SO–16
48 Units/Rail
NLAST4053DR2
SO–16
2500 Units/Reel
NLAST4053DT
TSSOP–16
96 Units/Rail
NLAST4053DTR2
TSSOP–16
2500 Units/Reel
NLAST4053QS
QSOP–16
98 Units/Rail
NLAST4053QSR
QSOP–16
2500 Units/Reel
Publication Order Number:
NLAST4053/D
NLAST4053
NOB
VCC
16
1
NOB
COMB COMC
15
14
2
3
NCB
NOA
NOC
NCC
13
12
4
5
AddC AddB
11
10
6
COMA NCA Inhibit
AddA
NCB
COMB
9
NOA
COMC
7
8
VEE
GND
COMA
NOC
NCA
NCC
Enable
C
Figure 1. Pin Connection
(Top View)
B
A
Figure 2. Logic Diagram
TRUTH TABLE
Address
Inhibit
ON SWITCHES*
C
B
A
1
X
don’t care
X
don’t care
X
don’t care
All switches open
0
0
0
0
COMA–NCA,
COMB–NCB,
COMC–NCC
0
0
0
1
COMA–NOA,
COMB–NCB,
COMC–NCC
0
0
1
0
COMA–NCA,
COMB–NOB,
COMC–NCC
0
0
1
1
COMA–NOA,
COMB–NOB,
COMC–NCC
0
1
0
0
COMA–NCA,
COMB–NCB,
COMC–NOC
0
1
0
1
COMA–NOA,
COMB–NCB,
COMC–NOC
0
1
1
0
COMA–NCA,
COMB–NOB,
COMC–NOC
0
1
1
1
COMA–NOA,
COMB–NOB,
COMC–NOC
*NO, NC, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
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2
NLAST4053
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MAXIMUM RATINGS (Note 1)
Value
Unit
VEE
Symbol
Negative DC Supply Voltage
Parameter
(Referenced to GND)
–7.0 to 0.5
V
VCC
Positive DC Supply Voltage (Note 2)
(Referenced to GND)
(Referenced to VEE)
–0.5 to 7.0
–0.5 to 7.0
V
VIS
Analog Input Voltage
VEE –0.5 to VCC 0.5
V
VIN
Digital Input Voltage
–0.5 to 7.0
V
I
DC Current, Into or Out of Any Pin
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
150
°C
JA
Thermal Resistance
SOIC
TSSOP
QSOP
143
164
164
°C/W
PD
Power Dissipation in Still Air,
SOIC
TSSOP
QSOP
500
450
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
2000
200
1000
V
ILATCH–UP
Latch–Up Performance
Above VCC and Below GND at 125°C (Note 6)
300
mA
(Referenced to GND)
50
mA
–65 to 150
°C
260
°C
Level 1
Oxygen Index: 30% – 35%
UL 94 V–0 @ 0.125 in
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. The absolute value of VCC |VEE| ≤ 7.0.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VEE
Negative DC Supply Voltage
(Referenced to GND)
–5.5
GND
V
VCC
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
2.5
2.5
5.5
6.6
V
VIS
Analog Input Voltage
VEE
VCC
V
VIN
Digital Input Voltage
0
5.5
V
TA
Operating Temperature Range, All Package Types
–55
125
°C
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
0
0
100
20
ns/V
(Note 7) (Referenced to GND)
VCC = 3.0 V 0.3 V
VCC = 5.0 V 0.5 V
7. Unused digital inputs may not be left open. All digital inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
NLAST4053
DC CHARACTERISTICS – Digital Section (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
–55 to 25°C
85°C
125°C
Unit
VIH
Minimum High–Level Input Voltage,
Address and Inhibit Inputs
3.0
4.5
5.5
1.6
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
VIL
Maximum Low–Level Input Voltage,
Address and Inhibit Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IIN
Maximum Input Leakage Current,
Address and Inhibit Inputs
VIN = 6.0 or GND
0 V to 6.0 V
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Address and Inhibit, and
VIS = VCC or GND
6.0
4.0
40
80
A
Symbol
Parameter
Condition
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DC ELECTRICAL CHARACTERISTICS – Analog Section
Symbol
Parameter
Test Conditions
RON
Maximum “ON” Resistance
VIN = VIL or VIH,
VIS = VEE to VCC
|IS| = 10 mA
(Figures 4 thru 9)
RON
Maximum Difference in “ON”
Resistance Between Any
Two Channels in the Same
Package
VIN = VIL or VIH,
|IS| = 10 mA,
VIS = 2.0 V
VIS = 3.0 V
VIS = 2.0 V
Guaranteed Limit
VCC
V
VEE
V
–55 to 25°C
85°C
125°C
Unit
3.0
4.5
3.0
0
0
–3.0
86
37
26
108
46
33
120
55
37
3.0
4.5
3.0
0
0
–3.0
15
2.0
10
20
2.0
15
20
2.0
15
0
–3.0
24
2.0
24
2.0
35
3.0
Rflat(ON)
COM–NO On–Resistance
Flatness
Vcom = 1, 2, 3.5 V
Vcom = –2, 0, 2 V
4.5
3.0
INC(OFF)
INO(OFF)
Maximum Off–Channel
Leakage Current
Switch Off
VIN = VIL or VIH
VIO = VCC –1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
–3.0
0.1
0.1
5.0
5.0
100
100
nA
ICOM(ON)
Maximum On–Channel
Leakage Current, Channel–
to–Channel
Switch On
VIO = VCC –1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
–3.0
0.1
0.1
5.0
5.0
100
100
nA
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4
NLAST4053
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AC CHARACTERISTICS (Input tr = tf = 3 ns)
Guaranteed Limit
Symbol
tBBM
Parameter
Minimum Break–Before–Make
Time
Test Conditions
VIN = VIL or VIH
VIS = VCC
RL = 300 CL = 35 pF
(Figure 19)
–55 to 25°C
VCC
V
VEE
V
Min
Typ*
85°C
125°C
Unit
3.0
4.5
3.0
0.0
0.0
–3.0
1.0
1.0
1.0
6.5
5.0
3.5
–
–
–
–
–
–
ns
*Typical Characteristics are at 25°C.
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
VEE
V
85°C
–55 to 25°C
Min
Typ
Max
Min
125°C
Max
Min
Max
Unit
tTRANS
Transition Time
(Address Selection Time)
(Figure 18)
2.5
3.0
4.5
3.0
0
0
0
–3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tON
Turn–on Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
–3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tOFF
Turn–off Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
–3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
Typical @ 25°C, VCC = 5.0 V
CIN
Maximum Input Capacitance,Select Inputs
8
CNO or CNC
Analog I/O
10
CCOM
Common I/O
10
C(ON)
Feedthrough
1.0
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5
pF
NLAST4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Condition
Typ
VCC
V
VEE
V
25°C
Unit
BW
Maximum On–Channel
Bandwidth or Minimum
Frequency Response
VIS = ½ (VCC – VEE)
Source Amplitude = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
–3.0
145
165
180
180
MHz
VISO
Off–Channel Feedthrough
Isolation
f = 100 kHz; VIS = ½ (VCC – VEE)
Source = 0 dBm
(Figures 12 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
–3.0
–93
–93
–93
–93
dB
VONL
Maximum Feedthrough
On Loss
VIS = ½ (VCC – VEE)
Source = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
–3.0
–2
–2
–2
–2
dB
Q
Charge Injection
VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 , CL= 1000 pF, Q = CL * VOUT
(Figures 16 and 23)
5.0
3.0
0.0
–3.0
9.0
12
pC
THD
Total Harmonic Distortion
THD + Noise
fIS = 1 MHz, RL = 10 K, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 13)
6.0
3.0
0.0
–3.0
0.10
0.05
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6
%
NLAST4053
100
100
10
2.0 V
80
RON ()
ICC (nA)
1
0.1
0.01
40
VCC = 3.0 V
0.001
3.0 V
3.3 V
4.5 V
5.5 V
20
0.0001
VCC = 5.0 V
0.00001
–40
–20
0
20
60
80
100
0
–4.0
120
–2.0
0
2.0
4.0
6.0
Temperature (°C)
VIS (VDC)
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 25C
50
100
125°C
90
125°C
85°C
40
80
25°C
70
60
RON ()
RON ()
60
50
85°C
40
25°C
30
20
–55°C
30
10
20
–55°C
10
0
0
0.5
1.0
1.5
0
2.0
1.0
1.5
2.0
2.5
VCom (V)
Figure 5. Typical On Resistance
VCC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
25
3.0
25
125°C
125°C
85°C
85°C
20
20
15
RON ()
RON ()
0.5
VCom (V)
10
25°C
15
25°C
10
–55°C
–55°C
5
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VCom (V)
VCom (V)
Figure 7. Typical On Resistance
VCC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
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7
5
5.5
NLAST4053
25
125°C
85°C
RON ()
20
15
10
–55°C
25°C
5
0
–4
–2
0
VCom (V)
2
4
Figure 9. Typical On Resistance
VCC = 3.0 V, VEE = –3.0 V
90
40
72
30
54
PHASE SHIFT (Deg)
BANDWIDTH (dB)
50
20
10
0
–10
BANDWIDTH (ON–RESPONSE)
–20
36
18
0
PHASE SHIFT
–18
–36
–30
–54
–40
–72
–90
–50
0.1
1.0
10
100
0.1
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth
Figure 11. Phase Shift
0
0
–20
–30
DISTORTION (%)
OFF ISOLATION 10 dB/DIV
–10
–40
–50
–60
–70
3.0
5.5
4.5
0.1
3.3
–80
–90
–100
0.01
0.1
1.0
10
100
10
FREQUENCY (mHz)
100
1000
10000
10000
FREQUENCY (mHz)
Figure 13. Total Harmonic Distortion
Figure 12. Off Isolation
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8
NLAST4053
30
30
VCC = 4.5 V
25
20
20
TIME (ns)
TIME (ns)
TA = 25°C
25
15
tON (ns)
10
tOFF (ns)
5
0
2.5
3
3.5
4
4.5
15
10
tON
5
tOFF
0
–55
5
–40
25
85
125
VCC (VOLTS)
Temperature (°C)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
100
2.5
10
VCC = 5 V
LEAKAGE (nA)
Q (pC)
2.0
1.5
1.0
0.5
1
ICOM(ON)
0.1
ICOM(OFF)
VCC = 3 V
0.01
0
VCC = 5.0 V
INO(OFF)
–0.5
0.001
0
1
2
3
4
5
–55
–20
25
70
85
125
VCOM (V)
TEMPERATURE (°C)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
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9
NLAST4053
VCC
0.1 F
VCC
Output
VOUT
VEE
300
Input
50%
50%
0V
35 pF
VCC
90%
Output
Address Select Pin
10%
VEE
ttrans
ttrans
Figure 18. Channel Selection Propagation Delay
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300
tBMM
35 pF
90%
90% of VOH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break–Before–Make)
VCC
DUT
VCC
0.1 F
Input
50%
0V
Output
VOUT
Open
300
50%
VOH
35 pF
90%
90%
Output
Input
GND
Enable
tON
Figure 20. tON/tOFF
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10
tOFF
NLAST4053
VCC
VCC
Input
DUT
Output
50%
0V
300
VOUT
Open
50%
VCC
35 pF
Output
Input
10%
VOL
Enable
tOFF
10%
tON
Figure 21. tON/tOFF
50
Reference
DUT
Transmitted
Input
Output
50 Generator
50
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
VVOUT
for VIN at 100 kHz
IN
VOUT
for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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11
NLAST4053
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
VIN
Off
On
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
16
VEE
GND
+3.0 V
VCC
16
VEE
7
8
GND
VCC
7
8
–3.0 V
Figure 24. 5.0 Volts Single Supply
VCC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = –3.0 V
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12
VOUT
NLAST4053
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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13
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
NLAST4053
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
–V–
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
G
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14
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
NLAST4053
PACKAGE DIMENSIONS
QSOP–16
M SUFFIX
CASE 492–01
ISSUE O
–A–
Q
R
H x 45
U
RAD.
0.013 X 0.005
DP. MAX
–B–
MOLD PIN
MARK
RAD.
0.005–0.010
TYP
G
L
0.25 (0.010)
M
P
T
DETAIL E
V
K
C
N 8 PL
–T–
D 16 PL
0.25 (0.010)
SEATING
PLANE
M
T B
S
A
S
J
M
F
DETAIL E
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15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
INCHES
DIM
MIN
MAX
A
0.189
0.196
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0
8
N
0
7
P
0.007
0.011
Q
0.020 DIA
R
0.025
0.035
U
0.025
0.035
8
V
0
MILLIMETERS
MIN
MAX
4.80
4.98
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0
8
0
7
0.18
0.28
0.51 DIA
0.64
0.89
0.64
0.89
0
8
NLAST4053
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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NLAST4053/D
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