NLHV4051DTR2G

NLHV4051, NLHV4052, NLHV4053 Analog Multiplexers/Demultiplexers The NLHV4051, NLHV4052, and NLHV4053 analog multiplexers are digitally−controlled analog switches. The NLHV4051 effectively implements an SP8T solid state switch, the NLHV4052 a DP4T, and the NLHV4053 a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. Features • • • • • • • • • • www.onsemi.com 1 Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage Range = 3.0 Vdc to 18 Vdc Analog Voltage Range (VDD − VEE) = 3.0 to 18 V Note: VEE must be ≤ VSS Linearized Transfer Characteristics Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical Pin−for−Pin Replacement for CD4051, CD4052, and CD4053 For 4PDT Switch, See MC14551B For Lower RON, Use the HC4051, HC4052, or HC4053 High−Speed CMOS Devices These Devices are Pb−Free and are RoHS Compliant 1 SOIC−16 D SUFFIX CASE 751B MARKING DIAGRAMS 16 NLHVG 405x AWLYWW 1 SOIC−16 16 NLHV 405x ALYWG G MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input Current (DC or Transient) per Control Pin +10 mA ISW Switch Through Current ±25 mA PD Power Dissipation per Package (Note 1) 500 mW Symbol VDD DC Supply Voltage Range (Referenced to VEE, VSS ≥ VEE) Vin, Vout Input or Output Voltage Range (DC or Transient) (Referenced to VSS for Control Inputs and VEE for Switch I/O) Iin TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) °C 260 TSSOP−16 DT SUFFIX CASE 948F 1 TSSOP−16 x A WL, L Y WW, W G or G = 1, 2, or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2016 April, 2017 − Rev. 0 1 Publication Order Number: NLHV4051/D NLHV4051, NLHV4052, NLHV4053 NLHV4051 8−Channel Analog Multiplexer/Demultiplexer CONTROLS SWITCHES IN/OUT 6 11 10 9 13 14 15 12 1 5 2 4 INHIBIT A B C X0 X1 X 3 X2 COMMON X3 OUT/IN X4 X5 X6 X7 NLHV4052 Dual 4−Channel Analog Multiplexer/Demultiplexer CONTROLS SWITCHES IN/OUT INHIBIT A X B X0 X1 X2 X3 Y0 Y Y1 Y2 Y3 6 10 9 12 14 15 11 1 5 2 4 NLHV4053 Triple 2−Channel Analog Multiplexer/Demultiplexer CONTROLS 13 COMMONS OUT/IN 3 SWITCHES IN/OUT INHIBIT X A B C X0 Y X1 Y0 Y1 Z Z0 Z1 6 11 10 9 12 13 2 1 5 3 COMMONS OUT/IN 15 4 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 14 Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS. PIN ASSIGNMENT NLHV4051 NLHV4052 NLHV4053 X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y X 3 14 X1 Y 3 14 X1 Z1 3 14 X X Z 4 13 X1 X7 4 13 X0 Y3 4 13 X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0 INH 6 11 A INH 6 11 X3 INH 6 11 A VEE 7 10 B VEE 7 10 A VEE 7 10 B VSS 8 9 C VSS 8 9 B VSS 8 9 C www.onsemi.com 2 NLHV4051, NLHV4052, NLHV4053 ELECTRICAL CHARACTERISTICS −55_C Characteristic Symbol VDD Test Conditions 25_C 125_C Min Max Min Typ (Note 2) 3.0 18 3.0 − 18 3.0 18 V − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mA Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) VDD – 3.0 ≥ VSS ≥ VEE Power Supply Voltage Range VDD − Quiescent Current Per Package IDD 5.0 10 15 Control Inputs: Vin = VSS or VDD, Switch I/O: VEE v VI/O v VDD, and DVswitch v 500 mV (Note 3) ID(AV) 5.0 10 15 TA = 25_C only (The channel component, (Vin – Vout)/Ron, is not included.) Total Supply Current (Dynamic Plus Quiescent, Per Package mA (0.07 mA/kHz) f + IDD (0.20 mA/kHz) f + IDD (0.36 mA/kHz) f + IDD Typical CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS) Low−Level Input Voltage VIL 5.0 10 15 Ron = per spec, Ioff = per spec − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 V High−Level Input Voltage VIH 5.0 10 15 Ron = per spec, Ioff = per spec 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − V Input Leakage Current Iin 15 Vin = 0 or VDD − ±0.1 − ±0.00001 ±0.1 − 1.0 mA Input Capacitance Cin − − − − 5.0 7.5 − − pF SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE) Recommended Peak−to−Peak Voltage Into or Out of the Switch VI/O − Channel On or Off 0 VDD 0 − VDD 0 VDD VPP Recommended Static or Dynamic Voltage Across the Switch (Note 3) (Figure 5) DVswitch − Channel On 0 600 0 − 600 0 300 mV Output Offset Voltage VOO − Vin = 0 V, No Load − − − 10 − − − mV ON Resistance Ron 5.0 10 15 DVswitch v 500 mV (Note 3) Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) − − − 800 400 220 − − − 250 120 80 1050 500 280 − − − 1200 520 300 W DRon 5.0 10 15 − − − 70 50 45 − − − 25 10 10 70 50 45 − − − 135 95 65 W Ioff 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel − ±100 − ±0.05 ±100 − ±1000 nA Capacitance, Switch I/O CI/O − Inhibit = VDD − − − 10 − − − pF Capacitance, Common O/I CO/I − Inhibit = VDD (NLHV4051) (NLHV4052) (NLHV4053) − − − − − − − − − 60 32 17 − − − − − − − − − Pins Not Adjacent Pins Adjacent − − − − − − 0.15 0.47 − − − − − − DON Resistance Between Any Two Channels in the Same Package Off−Channel Leakage Current (Figure 10) Capacitance, Feedthrough (Channel Off) CI/O − − pF pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. 3. For voltage drops across the switch (DVswitch) > 600 mV (> 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) www.onsemi.com 3 NLHV4051, NLHV4052, NLHV4053 ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated) Characteristic Propagation Delay Times (Figure 6) Switch Input to Switch Output (RL = 1 kW) NLHV4051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns Symbol VDD – VEE Vdc Typ (Note 5) All Types Max tPLH, tPHL ns 5.0 10 15 35 15 12 90 40 30 NLHV4052 tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns 5.0 10 15 30 12 10 75 30 25 NLHV4053 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 5.0 10 15 25 8.0 6.0 65 20 15 Inhibit to Output (RL = 10 kW, VEE = VSS) Output “1” or “0” to High Impedance, or High Impedance to “1” or “0” Level NLHV4051 Unit ns ns tPHZ, tPLZ, tPZH, tPZL ns 5.0 10 15 350 170 140 700 340 280 NLHV4052 5.0 10 15 300 155 125 600 310 250 ns NLHV4053 5.0 10 15 275 140 110 550 280 220 ns 5.0 10 15 360 160 120 720 320 240 NLHV4052 5.0 10 15 325 130 90 650 260 180 ns NLHV4053 5.0 10 15 300 120 80 600 240 160 ns − 10 0.07 − % BW 10 17 − MHz Off Channel Feedthrough Attenuation (Figure 7) RL = 1KW, Vin = 1/2 (VDD − VEE) p−p fin = 4.5 MHz — NLHV4051 fin = 30 MHz — NLHV4052 fin = 55 MHz — NLHV4053 − 10 –50 − dB Channel Separation (Figure 8) (RL = 1 kW, Vin = 1/2 (VDD−VEE) p−p, fin = 3.0 MHz − 10 –50 − dB Crosstalk, Control Input to Common O/I (Figure 9) (R1 = 1 kW, RL = 10 kW Control tTLH = tTHL = 20 ns, Inhibit = VSS) − 10 75 − mV Control Input to Output (RL = 1 kW, VEE = VSS) NLHV4051 Second Harmonic Distortion (RL = 10KW, f = 1 kHz) Vin = 5 VPP Bandwidth (Figure 7) (RL = 50 W, Vin = 1/2 (VDD−VEE) p−p, CL = 50pF 20 Log (Vout/Vin) = − 3 dB) tPLH, tPHL ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The formulas given are for the typical characteristics only at 25_C. 5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance. www.onsemi.com 4 NLHV4051, NLHV4052, NLHV4053 VDD VDD VDD IN/OUT OUT/IN VEE VDD LEVEL CONVERTED CONTROL IN/OUT OUT/IN CONTROL VEE Figure 1. Switch Circuit Schematic TRUTH TABLE 16 Control Inputs Select INH6 A11 B10 C9 ON Switches Inhibit C* B A NLHV4051 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 X0 X1 X2 X3 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 X4 X5 X6 X7 1 x x x None *Not applicable for MC14052 x = Don’t Care NLHV4052 Y0 Y1 Y2 Y3 X0 X1 X2 X3 NLHV4053 Z0 Z0 Z0 Z0 Y0 Y0 Y1 Y1 X0 X1 X0 X1 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 X0 X1 X0 X1 None VDD BINARY TO 1-OF-8 DECODER WITH INHIBIT LEVEL CONVERTER 8 X013 X114 7 VSS VEE X215 X312 3X X41 X55 None X62 X74 Figure 2. NLHV4051 Functional Diagram 16 VDD 16 INH6 BINARY TO 1-OF-4 DECODER WITH INHIBIT LEVEL CONVERTER A10 B9 8 X012 X114 VSS 7 INH6 A11 B10 C9 VEE X215 X311 Y01 Y15 Y22 Y34 BINARY TO 1-OF-2 DECODER WITH INHIBIT LEVEL CONVERTER 8 13X VDD VSS 7 VEE X012 X113 Y02 Y11 Z05 3Y Z13 Figure 3. NLHV4052 Functional Diagram Figure 4. NLHV4053 Functional Diagram www.onsemi.com 5 14X 15Y 4Z NLHV4051, NLHV4052, NLHV4053 TEST CIRCUITS ON SWITCH CONTROL SECTION OF IC A B C PULSE GENERATOR Vout LOAD V CL RL INH SOURCE VDD Figure 5. DV Across Switch VEE VEE VDD Figure 6. Propagation Delay Times, Control and Inhibit to Output A, B, and C inputs used to turn ON or OFF the switch under test. RL A B C VSS Vout INH A B C ON INH OFF CL = 50 pF RL Vout Vin RL CL = 50 pF VDD - VEE VDD - VEE 2 Vin 2 Figure 7. Bandwidth and Off−Channel Feedthrough Attenuation Figure 8. Channel Separation (Adjacent Channels Used For Setup) OFF CHANNEL UNDER TEST VDD A B C CONTROL SECTION OF IC Vout RL INH VEE OTHER CHANNEL(S) VEE VDD CL = 50 pF R1 COMMON VEE VDD Figure 9. Crosstalk, Control Input to Common O/I Figure 10. Off Channel Leakage NOTE: See also Figures 7 and 8 in the MC14016B data sheet. www.onsemi.com 6 NLHV4051, NLHV4052, NLHV4053 VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 kW RANGE VDD X-Y PLOTTER VEE = VSS Figure 11. Channel Resistance (RON) Test Circuit 350 300 300 250 200 150 TA = 125°C 100 25°C -55°C 50 0 -10 RON , “ON” RESISTANCE (OHMS) R ON , “ON” RESISTANCE (OHMS) 350 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 250 200 150 25°C -55°C 50 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 12. VDD = 7.5 V, VEE = − 7.5 V Figure 13. VDD = 5.0 V, VEE = − 5.0 V 700 350 600 300 500 400 300 TA = 125°C 200 25°C 100 0 -10 TA = 125°C 100 0 -10 10 R ON , “ON” RESISTANCE (OHMS) R ON , “ON” RESISTANCE (OHMS) TYPICAL RESISTANCE CHARACTERISTICS -55°C -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 VDD = 2.5 V 200 150 5.0 V 100 7.5 V 50 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 14. VDD = 2.5 V, VEE = − 2.5 V Figure 15. Comparison at 25°C, VDD = −VEE www.onsemi.com 7 10 TA = 25°C 250 0 -10 10 8.0 10 NLHV4051, NLHV4052, NLHV4053 APPLICATIONS INFORMATION Figure A illustrates use of the on−chip level converter detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control signal is used to directly control a 9 Vp−p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = +5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD − VSS = 5 V maximum swing above VSS ; VSS − VEE = 5 V maximum swing below VSS. The example shows a ±4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VEE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = +10 V, VSS = +5 V, and VEE – 3 V is acceptable. See the Table below. +5 V -5 V VDD VSS VEE + 4.5 V 9 Vp-p +5 V ANALOG SIGNAL EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNALS SWITCH I/O COMMON O/I NLHV4051 NLHV4052 NLHV4053 9 Vp-p ANALOG SIGNAL −4.5 V INHIBIT, A, B, C Figure A. Application Example VDD VDD DX DX ANALOG I/O COMMON O/I DX DX VEE VEE Figure B. External Germanium or Schottky Clipping Diodes POSSIBLE SUPPLY CONNECTIONS VDD In Volts VSS In Volts VEE In Volts Control Inputs Logic High/Logic Low In Volts Maximum Analog Signal Range In Volts +8 0 –8 +8/0 +8 to –8 = 16 Vp–p +5 0 –12 +5/0 +5 to –12 = 17 Vp–p +5 0 0 +5/0 +5 to 0 = 5 Vp–p +5 0 –5 +5/0 +5 to –5 = 10 Vp–p +10 +5 –5 +10/ +5 +10 to –5 = 15 Vp–p www.onsemi.com 8 GND NLHV4051, NLHV4052, NLHV4053 ORDERING INFORMATION Package Shipping† NLHV4051DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLHV4051DTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLHV4052DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLHV4052DTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLHV4053DR2G (In Development) SOIC−16 (Pb−Free) 2500 / Tape & Reel NLHV4053DTR2G (In Development) TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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