NLSX0102FCT2G

NLSX0102 2-Bit 20 Mb/s Dual-Supply Level Translator The NLSX0102 is a 2−bit configurable dual−supply bidirectional auto sensing translator that does not require a directional control pin. The I/O VCC and I/O VL ports are designed to track two different power supply rails, VCC and VL respectively. Both the VCC and VL supply rails are configurable from 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to be translated into lower, higher or equal value voltage logic signals on the VCC side, and vice−versa. The NLSX0102 translator has integrated 10 kW pull−up resistors on the I/O lines. The integrated pull−up resistors are used to pull−up the I/O lines to either VL or VCC. The NLSX0102 is an excellent match for open−drain applications such as the I2C communication bus. www.onsemi.com MARKING DIAGRAM A2 AAG AYWW A1 FLIP−CHIP 8 CASE 499BF A1 D1 Features • VL can be Less than, Greater than or Equal to VCC • Wide VCC Operating Range: 1.5 V to 5.5 V • • • • • • • AAG A Y WW Wide VL Operating Range: 1.5 V to 5.5 V High−Speed with 24 Mb/s Guaranteed Date Rate Low Bit−to−Bit Skew Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V Non−preferential Power−up Sequencing Integrated 10 kW Pull−up Resistors Small Space Saving Package − 1.9 mm x 0.9 mm x 0.5 mm Flipchip8 This is a Pb−Free Device = Specific Device Code = Assembly Location = Year = Work Week PIN ASSIGNMENTS I/O VCC2 A1 A2 I/O VCC1 GND B1 B2 VCC VL C1 C2 EN I/O VL2 D1 D2 I/O VL1 Typical Applications • I2C, SMBus • Low Voltage ASIC Level Translation • Mobile Phones, PDAs, Cameras (Top View) LOGIC DIAGRAM Important Information EN VL VCC GND • ESD Protection for All Pins − Human Body Model (HBM) > 7000 V I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2011 July, 2018 − Rev. 2 1 Publication Order Number: NLSX0102/D NLSX0102 VL VCC One−Shot Block PU1 One−Shot Block PU2 Gate Bias RPullup 10 kW RPullup 10 kW EN EN I/O VL I/O VCC N Figure 1. Block Diagram (1 I/O Line) PIN ASSIGNMENT Pins VCC VL GND EN I/O VCCn I/O VLn FUNCTION TABLE Description EN Operating Mode VCC Supply Voltage L Hi−Z VL Supply Voltage H I/O Buses Connected Ground Output Enable, referenced to VL I/O Port, referenced to VCC I/O Port, referenced to VL MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC High−side DC Supply Voltage −0.5 to +7.0 V VL Low−side DC Supply Voltage −0.5 to +7.0 V VCC−referenced DC Input / Output Voltage −0.5 to +7.0 V VL−referenced DC Input / Output Voltage −0.5 to +7.0 V Enable Control Pin DC Input Voltage −0.5 to +7.0 V I/O VCC I/O VL VEN II/O_SC Short−Circuit Duration (I/O VL and I/O VCC to GND) II/OK Input / Output Clamping Current (I/O VL and I/O VCC) TSTG Storage Temperature ±50 Continuous mA −50 VI/O < 0 mA −65 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 NLSX0102 RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC High−side Positive DC Supply Voltage Parameter 1.5 5.5 V VL Low−side Positive DC Supply Voltage 1.5 5.5 V VEN Enable Control Pin Voltage GND 5.5 V VIO I/O Pin Voltage GND 5.5 V Input Transition Rise and Fall Rate I/O VL and I/O VCC Ports, Push−Pull Driving 10 ns/V Control Input 10 Dt/DV TA Operating Temperature Range −40 +85 °C DC ELECTRICAL CHARACTERISTICS (TA = −40 to +85 °C, unless otherwise specified) −40 5C to +855C Symbol Parameter Test Conditions (Note 1) VL VCC Min VCC – 0.4 Typ (Notes 1, 2) Max Unit − V 0.15 V − V 0.15 V − V 0.35 * VL V − V 0.4 V − V VIHC I/O VCC Input HIGH Voltage 1.5 to 5.5 1.5 to 5.5 VILC I/O VCC Input LOW Voltage 1.5 to 5.5 1.5 to 5.5 VIHL I/O VL Input HIGH Voltage 1.5 to 5.5 1.5 to 5.5 VILL I/O VL Input LOW Voltage 1.5 to 5.5 1.5 to 5.5 VIH Control Pin Input HIGH Voltage 1.5 to 5.5 1.5 to 5.5 VIL Control Pin Input LOW Voltage 1.5 to 5.5 1.5 to 5.5 VOHC I/O VCC Output HIGH Voltage I/O VCC source current = −20 mA 1.5 to 5.5 1.5 to 5.5 VOLC I/O VCC Output LOW Voltage I/O VCC sink current = 1 mA 1.5 to 5.5 1.5 to 5.5 VOHL I/O VL Output HIGH Voltage I/O VL source current = −20 mA 1.5 to 5.5 1.5 to 5.5 VOLL I/O VL Output LOW Voltage I/O VL sink current = 1 mA 1.5 to 5.5 1.5 to 5.5 0.4 V IQVL VL Supply Current Supply Current I/O VCC and I/O VL unconnected, VEN = VL 1.5 to 5.5 1.5 to 5.5 2.0 mA 5.5 0 2.0 0 5.5 −1.0 1.5 to 5.5 1.5 to 5.5 2.0 5.5 0 2.0 0 5.5 −1.0 IQVCC ITS−VCC ITS−VL VL Supply Current Supply Current I/O VCC and I/O VL unconnected, VEN = VL VL – 0.4 0.65 * VL 2/3 * VCC 2/3 * VL mA VCC Tri−state Output Mode I/O VCC and I/O VL unconnected, VEN = GND 1.5 to 5.5 1.5 to 5.5 1.0 mA VL Tri−state Output Mode Supply Current I/O VCC and I/O VL unconnected, VEN = GND 1.5 to 5.5 1.5 to 5.5 1.0 mA 1. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. www.onsemi.com 3 NLSX0102 DC ELECTRICAL CHARACTERISTICS (TA = −40 to +85 °C, unless otherwise specified) −40 5C to +855C Parameter Symbol Test Conditions (Note 1) VL VCC Typ (Notes 1, 2) Min Max Unit II Enable Pin Input Leakage Current 1.5 to 5.5 1.5 to 5.5 1.0 mA IOZ I/O Tri−state Output Mode Leakage Current 1.5 to 5.5 1.5 to 5.5 1.0 mA RPU Pull−Up Resistors I/O VL and VC 10 kW 1. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. Timing Characteristics − Rail−to−Rail Driving Configuration (I/O test circuits of Figures 2, 3 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified) −405C to +855C VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Conditions Min Max Min Max Min Max Unit I/O VL Rise Time Figure 8 0.6 9.5 2.3 12.5 0.8 7.6 nS I/O VCC Rise Time Figure 8 4.0 10.8 2.7 9.1 2.7 7.6 nS I/O VL Fall Time Figure 8 2.0 9.7 1.9 8.1 1.7 13.3 nS I/O VCC Fall Time Figure 8 2.9 13.8 2.8 16.2 2.8 16.2 nS Propagation Delay (Driving I/O VL, VL to VCC) Figure 2 nS Propagation Delay (Driving I/O VCC, VCC to VL) Figure 3 tEN Enable Time tDIS Disable Time Symbol Parameter VL = 1.65 to 1.95 V tRVL tRVCC tFVL tFVCC tPHL−VL−VCC tPLH−VL−VCC tPHL−VCC−VL tPLH−VCC−VL tPPSKEW MDR 5.6 7.1 6.8 6.5 7.1 7.4 4.8 5.3 2.0 4.8 5.0 3.5 Figure 7 50 40 35 nS Figure 7 316 225 215 nS Part−to−Part Skew 0.7 Maximum Data Rate 21 0.7 22 0.7 24 nS nS Mbps VL = 2.3 to 2.7 V I/O VL Rise Time Figure 8 2.8 7.7 2.6 8.1 1.8 10.3 nS I/O VCC Rise Time Figure 8 3.2 9.2 2.9 8.8 2.4 6.4 nS I/O VL Fall Time Figure 8 1.9 8.3 1.9 7.8 1.8 7.4 nS I/O VCC Fall Time Figure 8 2.2 8.3 2.4 8.0 2.6 Propagation Delay (Driving I/O VL, VL to VCC) Figure 2 Propagation Delay (Driving I/O VCC, VCC to VL) Figure 3 tEN Enable Time tDIS Disable Time tRVL tRVCC tFVL tFVCC tPHL−VL−VCC tPLH−VL−VCC tPHL−VCC−VL tPLH−VCC−VL tPPSKEW MDR 10.0 nS 3.2 3.7 3.9 nS 4.8 5.3 6.0 2.5 1.6 1.0 4.5 4.3 3.4 Figure 7 50 40 35 nS Figure 7 225 225 215 nS 0.7 0.7 0.7 nS Part−to−Part Skew Maximum Data Rate 20 www.onsemi.com 4 22 24 nS Mbps NLSX0102 Timing Characteristics − Rail−to−Rail Driving Configuration (I/O test circuits of Figures 2, 3 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified) −405C to +855C VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Parameter Symbol Min Conditions Max Min Max Min Max Unit VL = 3.0 to 3.6 V I/O VL Rise Time Figure 8 2.3 6.5 1.9 8.0 nS I/O VCC Rise Time Figure 8 2.5 6.5 2.1 7.4 nS I/O VL Fall Time Figure 8 2.0 7.2 1.9 5.9 nS I/O VCC Fall Time Figure 8 2.3 8.0 2.4 9.3 nS Propagation Delay (Driving I/O VL, VL to VCC) Figure 2 2.4 3.1 nS 3.8 3.8 Propagation Delay (Driving I/O VCC, VCC to VL) Figure 3 2.5 2.6 3.6 3.1 tEN Enable Time Figure 7 40 35 nS tDIS Disable Time Figure 7 225 235 nS 0.7 0.7 nS tRVL tRVCC tFVL tFVCC tPHL−VL−VCC tPLH−VL−VCC tPHL−VCC−VL tPLH−VCC−VL tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 23 24 nS Mbps Timing Characteristics – Open Drain Driving Configuration (I/O test circuits of Figures 4, 5 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified) −405C to +855C VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Conditions Min Max Min Max Min Max Unit I/O VL Rise Time Figure 8 38 340 30 245 22.0 134 nS I/O VCC Rise Time Figure 8 34 330 23 218 10.0 120 nS I/O VL Fall Time Figure 8 4.4 11.1 4.3 12.0 4.2 14.2 nS I/O VCC Fall Time Figure 8 6.9 11 7.5 16.2 7.0 16.2 nS Propagation Delay (Driving I/O VL, VL to VCC) Figure 2 2.3 27 2.4 20.0 2.6 23.0 nS 45 260 36.0 208 27.0 208 Propagation Delay (Driving I/O VCC, VCC to VL) Figure 3 1.9 22 1.1 22.0 1.2 22.0 45.0 200 36 150 27.0 112 tEN Enable Time Figure 7 80 70 35 nS tDIS Disable Time Figure 7 250 277 290 nS 0.7 0.7 0.7 nS Symbol Parameter VL = 1.65 to 1.95 V tRVL tRVCC tFVL tFVCC tPHLVL−VCC tPLHVL−VCC tPHLVCC−VL tPLHVCC−VL tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 2 www.onsemi.com 5 2 2 nS Mbps NLSX0102 Timing Characteristics – Open Drain Driving Configuration (I/O test circuits of Figures 4, 5 and 7, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW, unless otherwise specified) −405C to +855C VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Parameter Symbol Conditions Min Max Min Max Min Max Unit VL = 2.3 to 2.7 V I/O VL Rise Time Figure 8 34 400 28.0 300 24.0 208 nS I/O VCC Rise Time Figure 8 35.0 352 24.0 280 12.0 180 nS I/O VL Fall Time Figure 8 4.4 6.9 4.3 6.2 4.2 7.8 nS I/O VCC Fall Time Figure 8 4.3 8.8 4.9 9.4 5.4 10.4 nS Propagation Delay (Driving I/O VL, VL to VCC) 1.7 14.0 2.0 14.0 2.1 14.0 Figure 2 43.0 250 36.0 210 27.0 210 Propagation Delay (Driving I/O VCC, VCC to VL) 1.8 13.0 2.6 13.0 1.2 13.0 Figure 3 44.0 225 37.0 180 27.0 144 tEN Enable Time Figure 7 50 40 35 nS tDIS Disable Time Figure 7 265 230 215 nS 0.7 0.7 0.7 nS tRVL tRVCC tFVL tFVCC tPHLVL−VCC tPLHVL−VCC tPHLVCC−VL tPLHVCC−VL tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 2 2 2 nS nS Mbps VL = 3.0 to 3.6 V I/O VL Rise Time Figure 8 25.0 400 19.0 278 nS I/O VCC Rise Time Figure 8 26.0 375 14.0 247 nS I/O VL Fall Time Figure 8 2.8 6.1 2.6 5.7 nS I/O VCC Fall Time Figure 8 2.6 7.6 3.1 8.3 nS Propagation Delay (Driving I/O VL, VL to VCC) 1.3 10.0 1.4 8.0 Figure 2 36.0 255 28.0 243 Propagation Delay (Driving I/O VCC, VCC to VL) 1.0 124 1.0 97.0 Figure 3 3.0 185 3.0 136 tEN Enable Time Figure 7 40 35 nS tDIS Disable Time Figure 7 250 205 nS 0.7 0.7 nS tRVL tRVCC tFVL tFVCC tPHLVL−VCC tPLHVL−VCC tPHLVCC−VL tPLHVCC−VL tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 2 www.onsemi.com 6 2 nS nS Mbps NLSX0102 TEST SETUPS NLSX0102 VL VCC NLSX0102 VL EN EN I/O VL I/O VCC Source I/O VL I/O VCC CLOAD CLOAD RLOAD NLSX0102 Figure 3. Rail−to−Rail Driving I/O VCC NLSX0102 VL VCC EN I/O VCC I/O VCC VCC CLOAD CLOAD RLOAD RLOAD Figure 4. Open−Drain Driving I/O VL Figure 5. Open−Drain Driving I/O VCC tRISE/FALL v 3 ns I/O VL tPD_VL−VCC I/O VCC VCC EN I/O VL 90% 50% 10% Source RLOAD Figure 2. Rail−to−Rail Driving I/O VL VL VCC tRISE/FALL v 3 ns I/O VCC 90% 50% 10% tPD_VCC−VL I/O VL tPD_VL− VCC 90% 50% 10% tPD_VCC−VL 90% 50% 10% tF−VCC tR−VCC tF−VL Figure 6. Definition of Timing Specification Parameters www.onsemi.com 7 tR−VL NLSX0102 VL VCC 2 x V* OPEN R1 PULSE GENERATOR DUT RT CL RL V* = VL or VCC Test Switch tPZH, tPHZ Open tPZL, tPLZ 2 x V* CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) V* = VL or VCC for I/O_VL or I/O_VCC measurements, respectively. Figure 7. Test Circuit for Enable/Disable Time Measurement tR tF 90% 50% 10% Input tPLH Output EN VCC GND GND tPZL tPHL 90% 50% 10% tR VL 50% Output Output HIGH IMPEDANCE 50% tPZH tF tPLZ tPHZ 10% VOL 90% VOH 50% Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement www.onsemi.com 8 HIGH IMPEDANCE NLSX0102 APPLICATIONS INFORMATION Level Translator Architecture of the device that is connected to the translator. The timing parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 kW. The NLSX0102 auto sense translator provides bi−directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX0102 consists of two bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. The one−shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high−to−low and low−to−high transitions. Each input/output channel has an internal 10 kW pull−up. The magnitude of the pull−up resistors can be reduced by connecting external resistors in parallel to the internal 10 kW resistors. Enable Input (EN) The NLSX0102 has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Overvoltage Tolerant (OVT) protection. Power Supply Guidelines During normal operation, supply voltage VL can be greater than, less than or equal to VCC. The sequencing of the power supplies will not damage the device during the power up operation. For optimal performance, 0.01 mF to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. Input Driver Requirements The rise (tR) and fall (tF) timing parameters of the open drain outputs depend on the magnitude of the pull−up resistors. In addition, the propagation times (tPD), skew (tPSKEW) and maximum data rate depend on the impedance ORDERING INFORMATION Package Shipping† NLSX0102FCT1G Flip−Chip 8 (Pb−Free) 3000 / Tape & Reel NLSX0102FCT2G Flip−Chip 8 (Pb−Free) 3000 / Tape & Reel (4mm Pitch Carrier Tape) NLSX0102FC2T2G Flip−Chip 8 (Pb−Free) 3000 / Tape & Reel (2mm Pitch Carrier Tape) Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 8 PIN FLIP−CHIP, 0.9x1.9, 0.5P CASE 499BF−01 ISSUE O A1 DATE 23 JUL 2009 SCALE 4:1 È È A B D PIN A1 REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. E DIM A A1 b D E e TOP VIEW A1 0.10 C A 8X GENERIC MARKING DIAGRAM* 0.05 C NOTE 3 C SIDE VIEW SEATING PLANE A2 XXXX AYWW e A1 e/2 8X b 0.05 C A B D 0.03 C B MILLIMETERS MIN MAX 0.50 0.44 0.15 0.19 0.21 0.25 0.90 BSC 1.90 BSC 0.50 BSC e XXXX A Y WW C A 1 2 e/2 BOTTOM VIEW D1 = Specific Device Code = Assembly Location = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 0.50 PITCH 0.50 PITCH A1 8X 0.25 PACKAGE OUTLINE *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON42381E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 8 PIN FLIP−CHIP, 0.9X1.9, 0.5P PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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