NLSX3012MUTAG

NLSX3012 2-Bit 100 Mb/s Configurable Dual-Supply Level Translator The NLSX3012 is a 2−bit configurable dual−supply bidirectional level translator without a direction control pin. The I/O VCC− and I/O VL−ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.3 V to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC − 0.4) V. This allows lower voltage logic signals on the VL side to be translated into higher voltage logic signals on the VCC side, and vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is required. The Output Enable (EN) input, when Low, disables both I/O ports by putting them in 3−state. This significantly reduces the supply currents from both VCC and VL. The EN signal is designed to track VL. MARKING DIAGRAMS UDFN8 MU SUFFIX CASE 517AJ 8 1 • Wide High−Side VCC Operating Range: 1.3 V to 4.5 V 8 SO−8 D SUFFIX CASE 751 1 Wide Low−Side VL Operating Range: 0.9 V to (VCC − 0.4) V High−Speed with 140 Mb/s Guaranteed Date Rate for VL > 1.8 V Low Bit−to−Bit Skew Overvoltage Tolerant Enable and I/O Pins Non−preferential Powerup Sequencing Small packaging: UDFN8, SO−8, Micro8 These are Pb−Free Devices Typical Applications A L Y W G SX3012 ALYW G G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 8 Micro8 DM SUFFIX CASE 846A 1 • Mobile Phones, PDAs, Other Portable Devices • PC and Laptops VAM G VA = Specific Device Code M = Date Code G = Pb−Free Package 8 Features • • • • • • http://onsemi.com 3012 AYW G G 1 A Y W G = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NLSX3012MUTAG UDFN8 3000/Tape & Reel (Pb−Free) NLSX3012DR2G SO−8 2500/Tape & Reel (Pb−Free) NLSX3012DMR2G Micro8 4000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 September, 2011 − Rev. 2 1 Publication Order Number: NLSX3012/D NLSX3012 LOGIC DIAGRAM VL EN VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 PIN ASSIGNMENTS VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 GND 4 UDFN8 (Top View) 5 EN 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN Micro8 (Top View) SOIC−8 (Top View) PIN ASSIGNMENT Pins I/O VCC2 VL FUNCTION TABLE Description EN Operating Mode VCC VCC Input Voltage L Hi−Z VL VL Input Voltage H I/O Buses Connected GND Ground EN Output Enable I/O VCCn I/O Port, Referenced to VCC I/O VLn I/O Port, Referenced to VL http://onsemi.com 2 NLSX3012 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC VCC Supply Voltage −0.5 to +5.5 V VL VL Supply Voltage −0.5 to +5.5 V I/O VCC VCC−Referenced DC Input/Output Voltage −0.5 to (VCC + 0.3) V I/O VL VL−Referenced DC Input/Output Voltage −0.5 to (VL + 0.3) V VEN Enable Control Pin DC Input Voltage −0.5 to +5.5 V IIK Input Diode Clamp Current −50 VI < GND mA IOK Output Diode Clamp Current −50 VO < GND mA ICC DC Supply Current Through VCC $100 mA IL DC Supply Current Through VL $100 mA IGND DC Ground Current Through Ground Pin $100 mA TSTG Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC VL Parameter Min Max Unit VCC Supply Voltage 1.3 4.5 V VL Supply Voltage 0.9 VCC − 0.4 V GND 4.5 V GND GND 4.5 4.5 V −40 +85 °C 0 10 ns VEN Enable Control Pin Voltage VIO Bus Input/Output Voltage TA Operating Temperature Range DI/DV I/O VCC I/O VL Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V P One−Shot VL +1.8V +3.6V VL +1.8 V System NLSX3012 4 kW VCC N One−Shot +3.6 V System I/O VL I/O1 I/O2 GND EN I/O VL1 VCC I/O VCC1 I/O1 I/O VL2 I/O VCC2 EN GND I/O2 I/O VCC P One−Shot GND 4 kW N One−Shot Figure 1. Typical Application Circuit Figure 2. Simplified Functional Diagram (1 I/O Line) (EN = 1) http://onsemi.com 3 NLSX3012 DC ELECTRICAL CHARACTERISTICS −405C to +855C Symbol Parameter Test Conditions (Note 1) VCC (V) (Note 2) VL (V) (Note 3) Min Typ (Note 4) Max Unit VIHC I/O VCC Input HIGH Voltage 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VCC − − V VILC I/O VCC Input LOW Voltage 1.3 to 4.5 0.9 to (VCC – 0.4) − − 0.2 * VCC V VIHL I/O VL Input HIGH Voltage 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL − − V VILL I/O VL Input LOW Voltage 1.3 to 4.5 0.9 to (VCC – 0.4) − − 0.2 * VL V VIH Control Pin Input HIGH Voltage TA = +25°C 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL − − V VIL Control Pin Input LOW Voltage TA = +25°C 1.3 to 4.5 0.9 to (VCC – 0.4) − − 0.2 * VL V VOHC I/O VCC Output HIGH Voltage I/O VCC Source Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VCC − − V VOLC I/O VCC Output LOW Voltage I/O VCC Sink Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4) − − 0.2 * VCC V VOHL I/O VL Output HIGH Voltage I/O VL Source Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL − − V VOLL I/O VL Output LOW Voltage I/O VL Sink Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4) − − 0.2 * VL V 1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V. 4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 4 NLSX3012 POWER CONSUMPTION Symbol Parameter Test Conditions (Note 5) VCC (V) (Note 6) VL (V) (Note 7) −405C to +855C Min Typ Max Unit IQ−VCC Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4) VCC I/O VCCn = VCC or I/O VLn = VL and Io = 0 − − 1.0 mA IQ−VL Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4) VL I/O VCCn = VCC or I/O VLn = VL and Io = 0 − − 1.0 mA − − 2.0 EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V, I/O VCCn = VCC or I/O VLn = (VCC − 0.2 V) and Io = 0 ITS−VCC ITS−VL IOZ IEN < (VCC – 0.2) VCC Tristate Output Mode Supply Current EN = 0 V 1.3 to 3.6 0.9 to (VCC – 0.4) − − 1.0 mA VL Tristate Output Mode Supply Current EN = 0 V 1.3 to 3.6 0.9 to (VCC – 0.4) − − 0.2 mA − − 2.0 I/O Tristate Output Mode Leakage Current EN = 0 V − − 0.15 − − 2.0 Output Enable Pin Input Current − − − 1.0 EN = 0 V VCC − 0.2 1.3 to 3.6 0.9 to (VCC – 0.4) EN = 0 V VCC – 0.2 1.3 to 3.6 0.9 to (VCC – 0.4) mA mA 5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V. 8. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 5 NLSX3012 TIMING CHARACTERISTICS −405C to +855C Symbol Parameter Test Conditions (Note 9) VCC (V) (Note 10) VL (V) (Note 11) Min Typ (Note 12) Max Unit tR−VCC I/O VCC Rise Time (Output = I/O_VCC) CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.7 2.4 ns tF−VCC I/O VCC Falltime (Output = I/O_VCC) CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.5 1.0 ns tR−VL I/O VL Risetime (Output = I/O_VL) CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 1.0 3.8 ns tF−VL I/O VL Falltime (Output = I/O_VL) CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.6 1.2 ns ZO−VCC I/O VCC One−Shot Output Impedance 1.3 to 4.5 0.9 to (VCC – 0.4) 30 W ZO−VL I/O VL One−Shot Output Impedance 1.3 to 4.5 0.9 to (VCC – 0.4) 30 W tPD_VL−VCC Propagation Delay (Output = I/O_VCC, tPHL, tPLH) CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 4.5 12 ns tPD_VCC−VL Propagation Delay (Output = I/O_VL, tPHL, tPLH) CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 3.0 7.2 ns Channel−to−Channel Skew (Output = I/O_VCC) CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 0.3 nS tSK_VCC−VL Channel−to−Channel Skew (Output = I/O_VL) CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 0.2 0.3 nS (Output = I/O_VCC, CIOVCC = 15 pF) (Output = I/O_VL, CIOVL = 15 pF) 1.3 to 4.5 0.9 to (VCC – 0.4) 110 > 2.2 > 1.8 140 tSK VL−VCC MDR Maximum Data Rate Mb/s 9. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 10. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 11. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V. 12. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 6 NLSX3012 ENABLE / DISABLE TIME MEASUREMENTS −405C to +855C tEN−VL Unit 0.9 to (VCC – 0.4) 150 200 ns 1.3 to 4.5 0.9 to (VCC – 0.4) 130 180 ns CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 95 225 ns CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 75 100 ns CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 175 250 ns CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 140 160 ns CIOVCC = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 180 275 ns CIOVL = 15 pF 1.3 to 4.5 0.9 to (VCC – 0.4) 160 220 ns VL (V) (Note 15) Turn−On Enable Time (Output = I/O_VCC, tpZH) CIOVCC = 15 pF 1.3 to 4.5 Turn−On Enable Time (Output = I/O_VCC, tpZL) CIOVL = 15 pF Turn−On Enable Time (Output = I/O_VL, tpZH) Turn−On Enable Time (Output = I/O_VL, tpZL) tDIS−VCC Turn−Off Disable Time (Output = I/O_VCC, tpHZ) Propagation Delay (Output = I/O_VCC, tPLZ) tDIS−VL Max VCC (V) (Note 14) Parameter tEN−VCC Typ (Note 16) Test Conditions (Note 13) Symbol Turn−Off Disable Time (Output = I/O_VL, tpHZ) Propagation Delay (Output = I/O_VL, tPLZ) Min 13. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 14. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 15. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V. 16. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 °C. All units are production tested at TA = +25 °C. Limits over the operating temperature range are guaranteed by design. NLSX3012 VL VCC NLSX3012 VL EN Source I/O VL VCC EN I/O VL I/O VCC I/O VCC CIOVL CIOVCC Source tRISE/FALL v 3 ns I/O VL 90% 50% 10% tPD_VL−VCC I/O VCC I/O VCC tRISE/FALL v 3 ns 90% 50% 10% tPD_VCC−VL I/O VL tPD_VL−VCC 90% 50% 10% tPD_VCC−VL 90% 50% 10% tF−VCC tR−VCC tF−VL Figure 3. Driving I/O VL Test Circuit and Timing tR−VL Figure 4. Driving I/O VCC Test Circuit and Timing http://onsemi.com 7 NLSX3012 VCC PULSE GENERATOR 2xVCC OPEN R1 DUT RT CL Test RL Switch tPZH, tPHZ Open tPZL, tPLZ 2 x VCC CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 5. Test Circuit for Enable/Disable Time Measurement tR tF Input tPLH Output 90% 50% 10% tR EN VCC 90% 50% 10% tPHL GND VL 50% tPZL Output 50% tPZH tF Output 50% GND tPLZ tPHZ HIGH IMPEDANCE 10% VOL 90% VOH Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement http://onsemi.com 8 HIGH IMPEDANCE NLSX3012 IMPORTANT APPLICATIONS INFORMATION translator options for an application such as the I2C bus that requires pullup resistors. Level Translator Architecture The NLSX3012 auto sense translator provides bi−directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX3012 consists of four bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. The one−shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high−to−low and low−to−high transitions. Enable Input (EN) The NLSX3012 has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over−Voltage Tolerant (OVT) protection. Uni−Directional versus Bi−Directional Translation The NLSX3012 can function as a non−inverting uni−directional translator. One advantage of using the translator as a uni−directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni−directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB. Input Driver Requirements Auto sense translators such as the NLSX3012 have a wide bandwidth, but a relatively small DC output current rating. The high bandwidth of the bi−directional I/O circuit is used to quickly transform from an input to an output driver and vice versa. The I/O ports have a modest DC current output specification so that the output driver can be over driven when data is sent to in the opposite direction. For proper operation, the input driver to the auto sense translator should be capable of driving 2 mA of peak output current with an output impedance less than 25 W. The bi−directional configuration of the translator results in both input stages being active for a very short time period. Although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard CMOS input stage. Power Supply Guidelines It is recommended that the VL supply should be less than or equal to the value of the VCC minus 0.4 V. The sequencing of the power supplies will not damage the device during the power up operation; however, the current consumption of the device will increase if VL exceeds VCC minus 0.4 V. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the power supply voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. Output Load Requirements The NLSX3012 is designed to drive CMOS inputs. Resistive pullup or pulldown loads of less than 50 kW should not be used with this device. The NLSX3373 or NLSX3378 open−drain auto sense translators are alternate http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8 1.8x1.2, 0.4P CASE 517AJ−01 ISSUE O 8 1 DATE 08 NOV 2006 SCALE 4:1 A B D ÉÉ ÉÉ 0.10 C PIN ONE REFERENCE 0.10 C L1 E DETAIL A NOTE 5 TOP VIEW (A3) 0.05 C DIM A A1 A3 b b2 D E e L L1 L2 A 0.05 C SIDE VIEW e/2 (b2) A1 e 1 4 8 5 C SEATING PLANE DETAIL A 8X L 8X b 0.10 M C A B 0.05 M C NOTE 3 MOUNTING FOOTPRINT SOLDERMASK DEFINED 8X 0.66 7X 0.22 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF GENERIC MARKING DIAGRAM* (L2) BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. XXM G XX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1.50 1 0.32 0.40 PITCH DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON23417D UDFN8 1.8X1.2, 0.4P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE K DATE 16 JUL 2020 SCALE 2:1 GENERIC MARKING DIAGRAM* 8 XXXX AYWG G 1 XXXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB14087C MICRO8 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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