NLSX4302EBMUTCG

2-Bit 20 Mb/s Dual-Supply Level Translator NLSX4302E The NLSX4302E is a 2−bit configurable dual−supply bidirectional auto sensing translator that does not require a directional control pin. The VCC I/O and VL I/O ports are designed to track two different power supply rails, VCC and VL respectively. Both the VCC and VL supply rails are configurable from 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to be translated into lower, higher or equal value voltage logic signals on the VCC side, and vice−versa. The NLSX4302E translator uses external pull−up resistors on the I/O lines. The external pull−up resistors are used to pull up the I/O lines to either VL or VCC. The NLSX4302E is an excellent match for open−drain applications such as the I2C communication bus. www.onsemi.com MARKING DIAGRAMS UQFN8 MU SUFFIX CASE 523AS E M Features • VL can be Less than, Greater than or Equal to VCC • Wide VCC Operating Range: 1.5 V to 5.5 V • • • • • • • Wide VL Operating Range: 1.5 V to 5.5 V High−Speed with 20 Mb/s Guaranteed Date Rate Low Bit−to−Bit Skew Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V Non−preferential Powerup Sequencing Power−Off Protection Small Space Saving Package: 1.4 mm x 1.2 mm UQFN8 Package These Devices are Pb−Free and are RoHS Compliant EM 1 = Specific Device Code = Date Code LOGIC DIAGRAM VL EN VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 Typical Applications • I2C, SMBus • Low Voltage ASIC Level Translation • Mobile Phones, PDAs, Cameras ORDERING INFORMATION Important Information • ESD Protection for All Pins − Human Body Model (HBM) > 6000 V − Machine Model (MM) > 400 V © Semiconductor Components Industries, LLC, 2012 August, 2021 − Rev. 1 Device Package Shipping† NLSX4302EBMUTCG UQFN8 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: NLSX4302E/D NLSX4302E Figure 1. Block Diagram (1 I/O Line) VL I/O VL1 2 I/O VL2 3 GND 4 1 5 8 VCC 7 I/O VCC1 6 I/O VCC2 EN UQFN8 (Top Through View) Figure 2. Pin−out Diagram PIN ASSIGNMENT Pins FUNCTION TABLE EN Operating Mode VCC VCC Supply Voltage Description L Hi−Z VL VL Supply Voltage H I/O Buses Connected GND Ground EN Output Enable, Referenced to VL I/O VCCn I/O Port, Referenced to VCC I/O VLn I/O Port, Referenced to VL www.onsemi.com 2 NLSX4302E MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC High−side DC Supply Voltage −0.3 to +7.0 V VL High−side DC Supply Voltage −0.3 to +7.0 V I/O VCC VCC−Referenced DC Input/Output Voltage −0.3 to (VCC + 0.3) V I/O VL VL−Referenced DC Input/Output Voltage −0.3 to (VL + 0.3) V VEN Enable Control Pin DC Input Voltage −0.3 to +7.0 V II/O_SC Short−Circuit Duration (I/O VL and I/O VCC to GND) TSTG Storage Temperature 40 Continuous mA −65 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC High−side Positive DC Supply Voltage 1.5 5.5 V VL High−side Positive DC Supply Voltage 1.5 5.5 V Enable Control Pin Voltage GND 5.5 V I/O Pin Voltage (Side referred to VCC) GND VCC V GND VL V 10 10 ns/V +85 °C VEN VIO_VCC Parameter VIO_VL I/O Pin Voltage (Side referred to VL) Dt/DV Input Transition Rise and Fall Rate TA I/O VL− or I/O VL− Ports, Push−Pull Driving Control Input Operating Temperature Range −40 www.onsemi.com 3 NLSX4302E DC ELECTRICAL CHARACTERISTICS (VL = 1.5 V to 5.5 V and VCC = 1.5 V to 5.5 V, unless otherwise specified) (Note 1) −405C to +855C Symbol VIH_VL VIH_VCC I/O High Level I/O_VCC VIL_VL Test Conditions (Note 2) Parameter I/O High Level I/O_VL I/O Low Level I/O_VL VIL_VCC I/O Low Level I/O_VCC VL (V) Min Typ Max 1.65–5.50 1.65–5.50 VL – 0.4 Control Input EN 1.65–5.50 1.65–5.50 VL x 0.7 Data Inputs I/O_VCCn 1.65–5.50 1.65–5.50 VCC – 0.4 Data Inputs I/O_VLn 1.65–5.50 1.65–5.50 0.4 Control Input EN 1.65–5.50 1.65–5.50 VL x 0.3 Unit V V V Data Inputs I/O_VCCn 1.65–5.50 1.65–5.50 0.4 V VOL Low Level Output Voltage VIL = 0.15 V, IOL = 6 mA 1.65–5.50 1.65–5.50 0.4 V IL Input Leakage Current Control Input EN, VIN = VL or GND 1.65–5.50 1.65–5.50 ±1 mA Power−Off Leakage Current I/O_VLn, I/O_VCCn ±2 mA ±2 mA IOFF VIN or VO = 0 to 5.5 V I/O_VLn I/O_VCCn IOZ Tristate Output Mode Leakage Current (Note 3) ICCZ 0 0 5.50 5.50 0 VO = 0 to 5.5 V, EN = VIL 5.50 5.50 I/O_VLn VO = 0 to 5.5 V, EN = Don’t Care 5.50 0 0 5.50 Quiescent Supply Current, Active Mode (Notes 4, 5) VL Quiescent Supply Current, Standby Mode (Notes 4, 5) VL ICC_OFF Quiescent Supply Current, Power−Off (Notes 3, 5) 0 I/O_VLn, I/O_VCCn I/O_VCCn ICC VCC VCC VL VCC 1. 2. 3. 4. 5. VCC (V) Data Inputs I/O_VLn VIN = VCCI or GND, IO = 0, EN = VIH_VL 1.65–5.50 1.65–5.50 5.0 mA VIN = VCCI or GND, IO = 0, EN = VIL_VL 1.65–5.50 1.65–5.50 5.0 mA 2.0 mA VIN = 5.5 V or GND, IO = 0, EN = Don’t Care, I/O_VCC to I/O_VL VIN = 5.5 V or GND, IO = 0, EN = Don’t Care, I/O_VL to I/O_VCC 0 1.65–5.50 1.65–5.50 0 1.65–5.50 0 0 1.65–5.50 Typical values are for VL = +1.8 V, VCC = +3.3 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. “Don’t care” indicates any valid logic level. VCCI is the power supply associated with the input side. Reflects current per supply, VL or VCC. www.onsemi.com 4 NLSX4302E DYNAMIC OUTPUT ELECTRICAL CHARACTERISTICS OUTPUT RISE / FALL TIMES (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 6) VCCO (Note 7) Parameter Symbol 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Typ Typ Typ Typ Unit tRISE Output Rise Time, I/O_VLn, I/O_VCCn 6.4 5 6.5 10.7 ns tFALL Output Fall Time, I/O_VLn, I/O_VCCn 10 9.5 8.6 9.5 ns 6. Output rise and fall times guaranteed by design and are not production tested. 7. VCCO is the VL or VCC power supply associated with the output side. MAXIMUM DATA RATE (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 8) VCC VL Parameter 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V I/O_VLn,to I/O_VCCn or I/O_VCCn to I/O_VLn 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Min Min Min Min Unit 50 41 31 17 MHz 34 35 36 23 MHz 25 27 30 24 MHz 14 16 22 21 MHz 8. Maximum frequency guaranteed by design and is not production tested. www.onsemi.com 5 NLSX4302E AC ELECTRICAL CHARACTERISTICS (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 9) VCC 4.5 to 5.5 V Symbol Parameter 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Typ Max Typ Max Typ Max Typ Max Unit VL = 4.5 to 5.5 V tPLH I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 2.5 4.3 3 5 3 6.4 4 8.6 ns tPHL I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 5 8.1 8 13 8 17.3 15 28.5 ns tPZL OE to I/O_Vln, OE to I/O_VCCn 14 19.6 16 20 22 26.5 33 44 ns tPLZ OE to I/O_Vln, OE to I/O_VCCn 24 31.4 25 32 24 31.8 28 36.2 ns tskew I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn (Note 10) 0.3 0.3 0.5 0.6 0.8 0.8 1.2 1.9 ns VL = 3.0 to 3.6 V tPLH I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 2.5 4.7 3 5.4 3 6.5 5 9.3 ns tPHL I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 7 14.2 6 10.1 8 14.6 15 27 ns tPZL OE to I/O_Vln, OE to I/O_VCCn 15 18.8 18 22.3 19 23.5 29 38.3 ns tPLZ OE to I/O_Vln, OE to I/O_VCCn 25 34.9 22 27.6 22 27.9 23 28.8 ns tskew I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn (Note 10) 0.4 0.5 0.5 0.6 0.6 0.7 2.5 3.0 ns VL = 2.3 to 2.7 V tPLH I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 3 5.6 4 6 4 7.3 6 10.3 ns tPHL I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 12 18.1 11 14.1 8 11.9 15 22.1 ns tPZL OE to I/O_Vln, OE to I/O_VCCn 16 23.7 17 21.5 25 30 31 36.6 ns tPLZ OE to I/O_Vln, OE to I/O_VCCn 28 33.8 26 31 25 30.8 25 30 ns tskew I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn (Note 10) 0.5 0.7 0.8 1 0.6 0.6 2.3 2.7 ns VL = 1.65 to 1.95 V tPLH I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 5 9 5 9.2 6 9.2 7 12.7 ns tPHL I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn 19 28.3 15 25.5 12 17.3 14 19 ns tPZL OE to I/O_Vln, OE to I/O_VCCn 23 32.2 22 26.5 25 32 40 72 ns tPLZ OE to I/O_Vln, OE to I/O_VCCn 35 44 32 38.7 33 36.7 30 36.5 ns tskew I/O_VLn to I/O_VCCn, I/O_VCCn to I/O_VLn (Note 10) 0.5 1.1 1.4 1.5 0.8 1.1 2.0 2.5 ns 9. AC characteristics are guaranteed by design and are not production tested. 10. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn) and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels. www.onsemi.com 6 NLSX4302E CAPACITANCE (TA = 25°C) Symbol Parameter Test Condition Typical Unit CIN Input Capacitance, Control Pin (EN) VL = VCC = GND 2 pF CIO Input / Output Capacitance (I/O_VLn, I/O_VCCn) VL = VCC = 5 V,EN = GND, I/O_VLn = I/O_VCCn = 5 V 3 pF CPD Power Dissipation Capacitance (Note 11) VL = VCC = 5 V,EN = 5 V, VIN = 5 V or GND, f = 400 KHz 17 pF 11. CPD is defined as the value of the internal equivalent capacitance per channel. TEST SETUP AND TIMING DEFINITIONS Figure 3. AC Test Circuit Figure 4. Propagation Delays and Tri-State Measurements Figure 5. Definition of Rise and Fall Times www.onsemi.com 7 NLSX4302E Figure 6. Definition of Output Skew Figure 7. Definition of Output Tri-State Times www.onsemi.com 8 NLSX4302E APPLICATIONS INFORMATION Level Translator Architecture when the transmitter is not transmitting data. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Overvoltage Tolerant (OVT) protection. The NLSX4302E auto sense translator provides bi−directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX4302E consists of two bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. The one−shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high−to−low and low−to−high transitions. Each input/output channel requires external pullup resistors. Power Supply Guidelines The sequencing of the power supplies will not damage the device during the power up operation. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 mF to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. Enable Input (EN) The NLSX4302E has an Enable pin (EN) that can be used to minimize the power consumption of the device www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UQFN8, 1.4x1.2, 0.4P CASE 523AS ISSUE B SCALE 4:1 DATE 19 AUG 2021 GENERIC MARKING DIAGRAM* XXM 1 XX = Specific Device Code M = Date Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON58906E UQFN8, 1.4X1.2, 0.4P Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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