NLSX4373
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4373 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The VCC I/O and VL I/O ports are designed to track two different
power supply rails, VCC and VL respectively. The VCC supply rail is
configurable from 1.5 V to 5.5 V while VL supply rail is configurable
to 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to
be translated into lower, higher or equal value voltage logic signals
on the VCC side, and vice−versa.
The NLSX4373 translator has open−drain outputs with integrated
10 kW pullup resistors on the I/O lines. The integrated pullup
resistors are used to pullup the I/O lines to either VL or VCC. The
NLSX4373 is an excellent match for open−drain applications such as
the I2C communication bus.
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MARKING
DIAGRAMS
UDFN8
MU SUFFIX
CASE 517AJ
8
1
VF = Specific Device Code
M = Date Code
G
= Pb−Free Package
8
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.5 V to 5.5 V
•
•
•
•
•
•
•
•
SO−8
D SUFFIX
CASE 751
8
1
Wide VL Operating Range: 1.5 V to 5.5 V
High−Speed with 20 Mb/s Guaranteed Date Rate
Low Bit−to−Bit Skew
Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to
5.5 V
Nonpreferential Powerup Sequencing
Integrated 10 kW Pullup Resistors
Small packaging: UDFN8, SO−8, Micro8
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
This is a Pb−Free Device
VFM
G
A
L
Y
W
G
SX4373
ALYW G
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
8
Micro8t
DM SUFFIX
CASE 846A
1
A
Y
W
G
4373
AYW G
G
1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Typical Applications
• I2C, SMBus, PMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
ORDERING INFORMATION
Device
Shipping†
NLSX4373MUTAG
UDFN8 3000/Tape & Reel
(Pb−Free)
NLVSX4373MUTAG*
UDFN8 3000/Tape & Reel
(Pb−Free)
NLSX4373DR2G
SO−8
2500/Tape & Reel
(Pb−Free)
NLVSX4373DR2G*
SO−8
2500/Tape & Reel
(Pb−Free)
NLSX4373DMR2G
Micro8
4000/Tape & Reel
(Pb−Free)
Important Information
• ESD Protection for All Pins
Package
− Human Body Model (HBM) > 7000 V
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 6
1
Publication Order Number:
NLSX4373/D
NLSX4373
LOGIC DIAGRAM
VL
EN
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
PIN ASSIGNMENTS
VL
1
8
VCC
I/O VL1
2
7
I/O VCC1
I/O VL2
3
6
I/O VCC2
GND
4
5
EN
VL 1
8
VCC
I/O VL1 2
7
I/O VCC1
I/O VL2 3
6
GND 4
UDFN8
(Top View)
5
EN
1
8
VCC
I/O VL1
2
7
I/O VCC1
I/O VL2
3
6
I/O VCC2
GND
4
5
EN
Micro8
(Top View)
SOIC−8
(Top View)
PIN ASSIGNMENT
Pins
I/O VCC2
VL
FUNCTION TABLE
Description
EN
Operating Mode
VCC
VCC Input Voltage
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
VCC I/O Port, Referenced to VCC
I/O VLn
VL I/O Port, Referenced to VL
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2
NLSX4373
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
High−side DC Supply Voltage
−0.3 to +7.0
V
VL
High−side DC Supply Voltage
−0.3 to +7.0
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.3 to (VCC + 0.3)
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.3 to (VL + 0.3)
V
VEN
Enable Control Pin DC Input Voltage
−0.3 to +7.0
V
II/O_SC
Short−Circuit Duration (I/O VL and I/O VCC to GND)
TSTG
Storage Temperature
40
Continuous
mA
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
High−side Positive DC Supply Voltage
1.5
5.5
V
VL
High−side Positive DC Supply Voltage
1.5
5.5
V
VEN
Enable Control Pin Voltage
GND
5.5
V
VIO
Enable Control Pin Voltage
GND
5.5
V
TA
Operating Temperature Range
−40
+85
°C
VL
VCC
PU1
RPullup
10 kW
One−Shot
Block
One−Shot
Block
Gate
Bias
EN
I/O VL
PU2
RPullup
10 kW
EN
I/O VCC
N
Figure 1. Block Diagram (1 I/O Line)
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3
NLSX4373
DC ELECTRICAL CHARACTERISTICS (VCC = 1.5 V to 5.5 V and VL = 1.5 V to 5.5 V, unless otherwise specified)
−405C to +855C
Symbol
Parameter
Test Conditions
Min
Typ
(Notes 1, 2)
Max
Unit
VCC − 0.4
−
−
V
VIHC
I/O VCC Input HIGH Voltage
VILC
I/O VCC Input LOW Voltage
−
−
0.15
V
VIHL
I/O VL Input HIGH Voltage
VL − 0.2
−
−
V
VILL
I/O VL Input LOW Voltage
−
−
0.15
V
VIH
Control Pin Input HIGH Voltage
VL − 0.2
−
−
V
VIL
Control Pin Input LOW Voltage
−
−
0.15
V
VOHC
I/O VCC Output HIGH Voltage
I/O VCC Source Current = 20 mA
2/3 * VCC
−
−
V
VOLC
I/O VCC Output LOW Voltage
I/O VCC Sink Current = 20 mA
−
−
1/3 * VCC
V
VOHL
I/O VL Output HIGH Voltage
I/O VL Source Current = 20 mA
2/3 * VL
−
−
V
VOLL
I/O VL Output LOW Voltage
I/O VL Sink Current = 20 mA
−
−
1/3 * VL
V
IQVCC
VCC Supply Current
I/O VCC and I/O VL Unconnected,
VEN = VL
−
0.5
2.0
mA
VL Supply Current
I/O VCC and I/O VL Unconnected,
VEN = VL
−
0.3
1.5
mA
VCC Tristate Output Mode Supply Current
I/O VCC and I/O VL Unconnected,
VEN = GND
−
0.1
1.0
mA
VL Tristate Output Mode Supply Current
I/O VCC and I/O VL Unconnected,
VEN = GND
−
0.1
1.0
mA
IQVL
ITS−VCC
ITS−VL
IOZ
I/O Tristate Output Mode Leakage Current
TA = +25°C
−
0.1
1.0
mA
RPU
Pullup Resistor I/O VL and VCC
TA = +25°C
−
10
−
kW
1. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C.
2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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4
NLSX4373
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 and 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 1.5 V, VCC = 5.5 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
20
ns
tRVL
I/O VL Risetime
30
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
20
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
20
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
Mb/s
VL = 1.8 V, VCC = 2.8 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
15
ns
tRVL
I/O VL Risetime
25
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
Mb/s
VL = 2.5 V, VCC = 3.6 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
Mb/s
VL = 2.8 V, VCC = 1.8 V
tRVCC
I/O VCC Risetime
25
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
20
ns
tFVL
I/O VL Falltime
15
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C.
4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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5
Mb/s
NLSX4373
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 and 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 3.6 V, VCC = 2.5 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
15
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
Mb/s
VL = 5.5 V, VCC = 1.5 V
tRVCC
I/O VCC Risetime
30
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
20
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
20
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
20
ns
Part−to−Part Skew
5
nS
tPPSKEW
Maximum Data Rate
20
Mb/s
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C.
4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 4 and 5, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 5 and 6)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
+1.5 v VL v VCC v +5.5 V
tRVCC
I/O VCC Risetime
400
ns
tFVCC
I/O VCC Falltime
50
ns
tRVL
I/O VL Risetime
400
ns
tFVL
I/O VL Falltime
60
ns
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
1000
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
1000
ns
50
nS
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
2
5. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C.
6. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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6
Mb/s
NLSX4373
TEST SETUPS
NLSX4373
VL
VCC
NLSX4373
VL
EN
Source
I/O VL
I/O VCC
I/O VL
I/O VCC
CLOAD
CLOAD
RLOAD
NLSX4373
Figure 3. Rail−to−Rail Driving I/O VCC
EN
I/O VCC
CLOAD
I/O VCC
VCC
CLOAD
RLOAD
Figure 4. Open−Drain Driving I/O VL
Figure 5. Open−Drain Driving I/O VCC
tRISE/FALL v
3 ns
tPD_VL−VCC
I/O VCC
VCC
EN
RLOAD
I/O VL
NLSX4373
VL
VCC
I/O VL
90%
50%
10%
Source
RLOAD
Figure 2. Rail−to−Rail Driving I/O VL
VL
VCC
EN
I/O VCC
tRISE/FALL v 3 ns
90%
50%
10%
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 6. Definition of Timing Specification Parameters
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7
tR−VL
NLSX4373
VCC
PULSE
GENERATOR
2xVCC
OPEN
R1
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 7. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
90%
50%
10%
tR
EN
VCC
90%
50%
10%
tPHL
GND
VL
50%
tPZL
Output
50%
tPZH
tF
Output
50%
GND
tPLZ
tPHZ
HIGH
IMPEDANCE
10%
VOL
90%
VOH
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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8
HIGH
IMPEDANCE
NLSX4373
APPLICATIONS INFORMATION
Level Translator Architecture
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 kW.
The NLSX4373 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX4373 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel has an internal 10 kW pull.
The magnitude of the pullup resistors can be reduced by
connecting external resistors in parallel to the internal
10 kW resistors.
Enable Input (EN)
The NLSX4373 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has Overvoltage
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage VL can be
greater than, less than or equal to VCC. The sequencing of
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (tPD), skew
(tPSKEW) and maximum data rate depend on the impedance
of the device that is connected to the translator. The timing
Micro8 is a trademark of International Rectifier.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8 1.8x1.2, 0.4P
CASE 517AJ−01
ISSUE O
8
1
DATE 08 NOV 2006
SCALE 4:1
A B
D
ÉÉ
ÉÉ
0.10 C
PIN ONE
REFERENCE
0.10 C
L1
E
DETAIL A
NOTE 5
TOP VIEW
(A3)
0.05 C
DIM
A
A1
A3
b
b2
D
E
e
L
L1
L2
A
0.05 C
SIDE VIEW
e/2
(b2)
A1
e
1
4
8
5
C
SEATING
PLANE
DETAIL A
8X
L
8X b
0.10
M
C A B
0.05
M
C
NOTE 3
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
8X
0.66
7X
0.22
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
0.30 REF
1.80 BSC
1.20 BSC
0.40 BSC
0.45
0.55
0.00
0.03
0.40 REF
GENERIC
MARKING DIAGRAM*
(L2)
BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
XXM
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.50
1
0.32
0.40 PITCH
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON23417D
UDFN8 1.8X1.2, 0.4P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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