ON Semiconductor
Is Now
To learn more about onsemi™, please visit our website at
www.onsemi.com
onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NLSX4402
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4402 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The VCC I/O and VL I/O ports are designed to track two different
power supply rails, VCC and VL respectively. Both the VCC and VL
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the VL side to be translated into lower, higher or
equal value voltage logic signals on the VCC side, and vice−versa.
The NLSX4402 translator has internal pull−up resistors on the I/O
lines. The pull−up resistors are used to pull up the I/O lines to either
VL or VCC. The NLSX4402 is an excellent match for open−drain
applications such as the I2C communication bus.
www.onsemi.com
MARKING
DIAGRAMS
UDFN8
1.45 x 1.0
CASE 517BZ
J
M
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.5 V to 5.5 V
•
•
•
•
•
Wide VL Operating Range: 1.5 V to 5.5 V
Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V
Non−preferential Powerup Sequencing
Power−Off Protection
Small Space Saving Packages:
1.45 mm x 1.0 mm UDFN8
1.8 mm x 1.2 mm X2DFN8
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
= Specific Device Code
= Date Code
X2DFN8
1.8 x 1.2
CASE 716AC
AAMG
G
AA = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
LOGIC DIAGRAM
VL
EN
• I2C, SMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
JM
1
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 5000 V
ORDERING INFORMATION
Package
Shipping†
NLSX4402FMUTCG
UDFN8
(Pb−Free)
3000 / Tape &
Reel
NLSX4402MX2ATAG
(In Development)
X2DFN8
(Pb−Free)
3000 / Tape &
Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
© Semiconductor Components Industries, LLC, 2017
August, 2017 − Rev. 3
1
Publication Order Number:
NLSX4402/D
NLSX4402
Figure 1. Block Diagram (1 I/O Line)
VL
1
8
VCC
I/O VL1
2
7
I/O VCC1
I/O VL2
3
6
I/O VCC2
GND
4
5
EN
UDFN8 / X2DFN8
(Top Through View)
Figure 2. Pinout Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
EN
Operating Mode
VCC
VCC Supply Voltage
Description
L
Hi−Z
VL
VL Supply Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable, Referenced to VL
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
www.onsemi.com
2
NLSX4402
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
High−side DC Supply Voltage
−0.5 to +7.0
V
VL
High−side DC Supply Voltage
−0.5 to +7.0
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to +7.0
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to +7.0
V
VEN
Enable Control Pin DC Input Voltage
−0.5 to +7.0
V
II/O_SC
Short−Circuit Duration (I/O VL and I/O VCC to GND)
±50
Continuous
mA
II/OK
Input/Output Clamping Current (I/O VL and I/O VCC)
−50
VI/O < 0
mA
TSTG
Storage Temperature
°C
−65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
High−side Positive DC Supply Voltage
1.5
5.5
V
VL
High−side Positive DC Supply Voltage
1.5
5.5
V
Enable Control Pin Voltage
GND
5.5
V
VEN
VIO_VCC
I/O Pin Voltage (Side referred to VCC)
GND
5.5
V
VIO_VL
I/O Pin Voltage (Side referred to VL)
GND
5.5
V
Dt/DV
Input Transition Rise and Fall Rate
10
10
ns/V
+85
°C
TA
A− or B−Ports, Push−Pull Driving
Control Input
Operating Temperature Range
−40
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
3
NLSX4402
DC ELECTRICAL CHARACTERISTICS (VL = 1.5 V to 5.5 V and VCC = 1.5 V to 5.5 V, unless otherwise specified) (Note 1)
−405C to +855C
Symbol
Parameter
Test Conditions (Note 2)
Min
Typ
Max
Unit
VIHC
I/O VCC Input HIGH Voltage
VCC – 0.4
−
−
V
VILC
I/O VCC Input LOW Voltage
−
−
0.15
V
VIHL
I/O VL Input HIGH Voltage
VL – 0.4
−
−
V
VILL
I/O VL Input LOW Voltage
−
−
0.15
V
VIH
Control Pin Input HIGH Voltage
0.65 * VL
−
−
V
VIL
Control Pin Input LOW Voltage
−
−
0.35 * VL
V
2/3 * VCC
−
−
V
−
−
0.4
V
2/3 * VL
−
−
V
VOHC
I/O VCC Output HIGH Voltage
I/O VCC source current = 20 mA
VOLC
I/O VCC Output LOW Voltage
I/O VCC sink current = 1 mA
VOHL
I/O VL Output HIGH Voltage
I/O VL source current = 20 mA
VOLL
I/O VL Output LOW Voltage
I/O VL sink current = 1 mA
−
−
0.4
V
IQVCC
VCC Supply Current
I/O VCC and I/O VL unconnected, VEN = VL
VL = 5.5 V, VCC = 0 V
VL = 0 V, VCC = 5.5 V
−
−
−
0.5
−
−
2.0
1.0
−1.0
mA
I/O VCC and I/O VL unconnected, VEN = VL
VL = 5.5 V, VCC = 0 V
V = 0 V, V
L
CC = 5.5 V
−
−
−
0.3
−
−
1.5
−1.0
1.0
mA
I/O VCC and I/O VL unconnected, VEN = GND
−
0.1
1.0
mA
I/O VCC and I/O VL unconnected, VEN = GND
−
0.1
1.0
mA
−
−
1.0
mA
I/O VCC Port, VCC = 0 V, VL = 0 to 5.5 V
−
−
1.0
mA
I/O VL Port, VCC = 0 to 5.5 V, VL = 0 V
Supply Current
IQVL
VL Supply Current
Supply Current
ITS−VCC VCC Tristate Output Mode
ITS−VL
II
VL Tristate Output Mode Supply Current
Enable Pin Input Leakage Current
IOFF
I/O Power-Off Leakage Current
−
−
1.0
IOZ
I/O Tristate Output Mode
Leakage Current
−
0.1
1.0
mA
RPU
Pull−Up Resistors
I/O VL and VC
−
10
−
kΩ
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Typical values are for VL = +1.8 V, VCC = +3.3 V and TA = +25°C.
2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
www.onsemi.com
4
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 3 and 4, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 & 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 1.5 V, VCC = 1.5 V
tRVCC
I/O VCC Rise Time
9
32
ns
tFVCC
I/O VCC Fall Time
11
20
ns
tRVL
I/O VL Rise Time
20
30
ns
tFVL
I/O VL Fall Time
10
13
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
7
16
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
12
15
ns
tEN
Enable Time
50
ns
tDIS
Disable Time
300
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
15
Mbps
VL = 1.5 V, VCC = 5.5 V
tRVCC
I/O VCC Rise Time
9
12
ns
tFVCC
I/O VCC Fall Time
17
30
ns
tRVL
I/O VL Rise Time
2
4
ns
tFVL
I/O VL Fall Time
3
7
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
14
24
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
3
5
ns
tEN
Enable Time
40
ns
tDIS
Disable Time
250
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
20
Mbps
VL = 1.8 V, VCC = 2.8 V
tRVCC
I/O VCC Rise Time
11
18
ns
tFVCC
I/O VCC Fall Time
10
15
ns
tRVL
I/O VL Rise Time
12
15
ns
tFVL
I/O VL Fall Time
5
8
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
7
10
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
5
9
ns
tEN
Enable Time
50
ns
tDIS
Disable Time
300
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
20
Mbps
VL = 2.5 V, VCC = 3.6 V
tRVCC
I/O VCC Rise Time
8
12
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
5
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 & 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 2.5 V, VCC = 3.6 V
tFVCC
I/O VCC Fall Time
8
12
ns
tRVL
I/O VL Rise Time
7
10
ns
tFVL
I/O VL Fall Time
5
7
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
7
10
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
5
8
ns
tEN
Enable Time
40
ns
tDIS
Disable Time
225
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
24
Mbps
VL = 2.8 V, VCC = 1.8 V
tRVCC
I/O VCC Rise Time
13
20
ns
tFVCC
I/O VCC Fall Time
7
10
ns
tRVL
I/O VL Rise Time
8
13
ns
tFVL
I/O VL Fall Time
9
15
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
6
9
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
7
12
ns
tEN
Enable Time
60
ns
tDIS
Disable Time
250
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
24
Mbps
VL = 3.6 V, VCC = 2.5 V
tRVCC
I/O VCC Rise Time
9
12
ns
tFVCC
I/O VCC Fall Time
6
9
ns
tRVL
I/O VL Rise Time
6
12
ns
tFVL
I/O VL Fall Time
7
12
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
5
7
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
6
9
ns
tEN
Enable Time
50
ns
tDIS
Disable Time
250
ns
tPPSKEW
MDR
Part−to−Part Skew
2
Maximum Data Rate
24
ns
Mbps
VL = 5.5 V, VCC = 1.5 V
tRVCC
I/O VCC Rise Time
13
20
ns
tFVCC
I/O VCC Fall Time
6
9
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
6
NLSX4402
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 & 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 5.5 V, VCC = 1.5 V
tRVL
I/O VL Rise Time
8
10
ns
tFVL
I/O VL Fall Time
20
27
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
5
8
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
14
24
ns
tEN
Enable Time
ns
tDIS
Disable Time
ns
tPPSKEW
MDR
Part−to−Part Skew
2
Maximum Data Rate
20
ns
Mbps
VL = 5.5 V, VCC = 5.5 V
tRVCC
I/O VCC Rise Time
5
7
ns
tFVCC
I/O VCC Fall Time
6
8
ns
tRVL
I/O VL Rise Time
5
7
ns
tFVL
I/O VL Fall Time
4
7
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
4
6
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
4
6
ns
tEN
Enable Time
30
ns
tDIS
Disable Time
225
ns
tPPSKEW
MDR
Part−to−Part Skew
2
Maximum Data Rate
24
ns
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 5 and 6, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 6 & 7)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 1.5 V, VCC = 1.5 V
tRVCC
I/O VCC Rise Time
55
70
ns
tFVCC
I/O VCC Fall Time
7
14
ns
tRVL
I/O VL Rise Time
50
65
ns
tFVL
I/O VL Fall Time
7
12
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
7
NLSX4402
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 6 & 7)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 1.5 V, VCC = 1.5 V
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
20
34
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
19
34
ns
tEN
Enable Time
100
ns
tDIS
Disable Time
300
ns
tPPSKEW
MDR
Part−to−Part Skew
2
Maximum Data Rate
3
ns
Mbps
VL = 1.5 V, VCC = 5.5 V
tRVCC
I/O VCC Rise Time
22
34
ns
tFVCC
I/O VCC Fall Time
20
27
ns
tRVL
I/O VL Rise Time
43
55
ns
tFVL
I/O VL Fall Time
6
12
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
13
26
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
19
24
ns
tEN
Enable Time
80
ns
tDIS
Disable Time
250
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
3
Mbps
VL = 1.8 V, VCC = 3.3 V
tRVCC
I/O VCC Rise Time
34
40
ns
tFVCC
I/O VCC Fall Time
1
15
ns
tRVL
I/O VL Rise Time
40
48
ns
tFVL
I/O VL Fall Time
1
2
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
9
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
6
11
ns
tEN
Enable Time
70
ns
tDIS
Disable Time
300
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
7
Mbps
VL = 5.5 V, VCC = 1.5 V
tRVCC
I/O VCC Rise Time
44
52
ns
tFVCC
I/O VCC Fall Time
1
2
ns
tRVL
I/O VL Rise Time
7
30
ns
tFVL
I/O VL Fall Time
17
23
ns
Propagation Delay (Driving I/O VL, VL to VCC)
10
17
ns
tPDVL−VCC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
8
NLSX4402
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, CLOAD = 15 pF, driver output impedance ≤ 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 6 & 7)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
12
24
ns
VL = 5.5 V, VCC = 1.5 V
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
tEN
Enable Time
100
ns
tDIS
Disable Time
300
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
3
Mbps
VL = 5.5 V, VCC = 5.5 V
tRVCC
I/O VCC Rise Time
42
50
ns
tFVCC
I/O VCC Fall Time
2
3
ns
tRVL
I/O VL Rise Time
44
48
ns
tFVL
I/O VL Fall Time
2
3
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL, VL to VCC)
4
6
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC, VCC to VL)
6
9
ns
tEN
Enable Time
60
ns
tDIS
Disable Time
225
ns
2
ns
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
7
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified VL and VCC at TA = +25°C. All units are production tested at TA = +25°C.
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
9
NLSX4402
TEST SETUP
NLSX4402
VL
VCC
NLSX4402
VL
EN
I/O VL
I/O VCC
Source
I/O VL
I/O VCC
CLOAD
CLOAD
RLOAD
NLSX4402
Figure 4. Rail−to−Rail Driving I/O VCC,
VCC to VL
NLSX4402
VL
VCC
EN
I/O VCC
VCC
CLOAD
CLOAD
RLOAD
RLOAD
Figure 5. Open−Drain Driving I/O VL,
VL to VCC
Figure 6. Open−Drain Driving I/O VCC,
VCC to VL
tRISE/FALL v
3 ns
I/O VL
tPD_VL−VCC
I/O VCC
VCC
EN
I/O VCC
I/O VL
90%
50%
10%
Source
RLOAD
Figure 3. Rail−to−Rail Driving I/O VL,
VL to VCC
VL
VCC
EN
tRISE/FALL v 3 ns
I/O VCC
90%
50%
10%
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 7. Definition of Timing Specification Parameters
www.onsemi.com
10
tR−VL
NLSX4402
VCC
2xVCC
OPEN
R1
PULSE
GENERATOR
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 8. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
EN
VCC
90%
50%
10%
GND
GND
tPZL
tPHL
90%
50%
10%
tR
VL
50%
Output
Output
HIGH
IMPEDANCE
50%
tPZH
tF
tPLZ
tPHZ
10%
VOL
90%
VOH
50%
Figure 9. Timing Definitions for Propagation Delays and Enable/Disable Measurement
www.onsemi.com
11
HIGH
IMPEDANCE
NLSX4402
APPLICATIONS INFORMATION
Level Translator Architecture
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 kW.
The NLSX4402 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX4402 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel has an internal 10 kW pull.
The magnitude of the pullup resistors can be reduced by
connecting external resistors in parallel to the internal
10 kW resistors.
Enable Input (EN)
The NLSX4402 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has Overvoltage
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage VL can be
greater than, less than or equal to VCC. The sequencing of
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (tPD), skew
(tPSKEW) and maximum data rate depend on the impedance
of the device that is connected to the translator. The timing
www.onsemi.com
12
NLSX4402
PACKAGE DIMENSIONS
UDFN8, 1.45x1, 0.35P
CASE 517BZ
ISSUE O
PIN ONE
REFERENCE
0.10 C
2X
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
A B
D
ÏÏ
ÏÏ
ÏÏ
E
DIM
A
A1
A3
b
D
E
e
L
L1
TOP VIEW
A3
0.05 C
A
0.05 C
A1
SIDE VIEW
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
7X
e/2
e
1
7X
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.45 BSC
1.00 BSC
0.35 BSC
0.25
0.35
0.30
0.40
0.48
L
8X
0.22
4
L1
1.18
8
5
BOTTOM VIEW
8X
b
0.10
M
C A B
0.05
M
C
0.53
1
PKG
OUTLINE
NOTE 3
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
NLSX4402
PACKAGE DIMENSIONS
X2DFN8 1.8x1.2, 0.4P
CASE 716AC
ISSUE O
ÏÏ
ÏÏ
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
D
E
TOP VIEW
DETAIL B
DIM
A
A1
A3
b
D
E
e
K
L
A3
0.05 C
0.05 C
NOTE 4
SIDE VIEW
C
A1
DETAIL B
SEATING
PLANE
8X L
1
MILLIMETERS
MIN
NOM MAX
0.34
0.37
0.40
−−−
−−−
0.05
0.127 REF
0.15
0.20
0.25
1.70
1.80
1.90
1.10
1.20
1.30
0.40 BSC
0.20 REF
0.45
0.50
0.55
RECOMMENDED
SOLDERING FOOTPRINT*
4
8X
0.65
K
8
5
8X
e
e/2
BOTTOM VIEW
b
PACKAGE
OUTLINE
0.10 C A B
0.05 C
1.50
NOTE 3
1
8X
0.40
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent− Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
◊
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
14
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NLSX4402/D
