NLSX5014
4-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX5014 is a 4-bit configurable dual-supply autosensing
bidirectional level translator that does not require a direction control
pin. The I/O VCC- and I/O VL-ports are designed to track two
different power supply rails, VCC and VL respectively. Both the VCC
and the VL supply rails are configurable from 0.9 V to 4.5 V. This
allows a logic signal on the VL side to be translated to either a higher
or a lower logic signal voltage on the VCC side, and vice-versa.
The NLSX5014 offers the feature that the values of the VCC and
VL supplies are independent. Design flexibility is maximized
because VL can be set to a value either greater than or less than the
VCC supply. In contrast, the majority of competitive auto sense
translators have a restriction that the value of the VL supply must be
equal to less than (VCC - 0.4) V.
The NLSX5014 has high output current capability, which allows the
translator to drive high capacitive loads such as most high frequency
EMI filters. Another feature of the NLSX5014 is that each I/O_VLn and
I/O_VCCn channel can function as either an input or an output.
An Output Enable (EN) input is available to reduce the power
consumption. The EN pin can be used to disable both I/O ports by
putting them in 3-state which significantly reduces the supply current
from both VCC and VL. The EN signal is referenced to the VL supply.
− VL may be greater than, equal to, or less than VCC
High 100 pF Capacitive Drive Capability
High−Speed with 140 Mb/s Guaranteed Date Rate
for VCC, VL > 1.8 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Powerup Sequencing
Power−Off Protection
Small packaging: 1.7 mm x 2.0 mm UQFN12, SOIC14, TSSOP14
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
• ESD Protection for All Pins:
HBM (Human Body Model) > 7000 V
© Semiconductor Components Industries, LLC, 2014
April, 2018 − Rev. 8
1
M
G
AAMG
G
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
14
SOIC−14
D SUFFIX
CASE 751A
14
1
NLSX5014G
AWLYWW
1
14
TSSOP−14
DT SUFFIX
CASE 948G
14
NLSX
5014
ALYWG
G
A
=
Assembly Location
WL, L
=
Wafer Lot
YY, Y
=
Year
WW, W =
Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NLSX5014MUTAG
UQFN12 3000/Tape & Reel
(Pb−Free)
NLSX5014DR2G
SO−14
2500/Tape & Reel
(Pb−Free)
NLSX5014DTR2G
TSSOP14 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Important Information
♦
UQFN12
MU SUFFIX
CASE 523AE
1
• Wide VCC, VL Operating Range: 0.9 V to 4.5 V
• VL and VCC are independent
•
•
•
•
•
•
MARKING
DIAGRAMS
1
Features
•
•
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1
Publication Order Number:
NLSX5014/D
NLSX5014
P
One−Shot
VL
+1.8V
VCC
R1
+3.6V
1k
VL
+1.8 V System
I/O1
I/On
GND OE
NLSX5014
I/O VL1
N
One−Shot
VCC
+3.6 V System
I/O VCC1
I/O1
I/O VLn I/O VCCn
EN
GND
I/On
I/O VL
I/O VCC
P
One−Shot
R2
GND
1k
N
One−Shot
Figure 1. Typical Application Circuit
2.5 V
VL
mC
NLSX5014
VCC
3.0 V
2.5 V
Temperature
Sensor
mC
CE
I/O VL1
I/O VCC1
CE
SCK
I/O VL2
I/O VCC2
SDO
I/O VL3
SDI
I/O VL4
ANO
EN
Figure 2. Simplified Functional Diagram (1 I/O Line)
1.8 V
VL
NLSX5014
VCC
Temperature
Sensor
CE
I/O VL1
I/O VCC1
CE
SCK
SCK
I/O VL2
I/O VCC2
SCK
I/O VCC3
SDI
SDO
I/O VL3
I/O VCC3
SDI
I/O VCC4
SDO
SDI
I/O VL4
I/O VCC4
SDO
GND
ANO
Figure 3. Application Example for VL < VCC
EN
GND
Figure 4. Application Example for VL > VCC
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2
NLSX5014
EN
VL
1
I/O VL1
VL
1
14
EN
I/O VL1
2
13
VCC
11
VCC
I/O VL2
3
12
I/O VCC1
2
10
I/O VCC1
I/O VL3
4
11
I/O VCC2
I/O VL2
3
9
I/O VCC2
10
I/O VCC3
4
8
I/O VCC3
I/O VL4
5
I/O VL3
I/O VL4
5
7
I/O VCC4
NC
6
9
NC
GND
7
8
I/O VCC4
12
6
GND
UQFN12
(Top View)
TSSOP/SOIC
(Top View)
Figure 1. Pin Assignments
VL
EN
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
Figure 2. Logic Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
EN
Operating Mode
VCC
VCC Input Voltage
Description
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
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3
NLSX5014
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
High−side DC Supply Voltage
−0.5 to +5.5
V
VL
Low−side DC Supply Voltage
−0.5 to +5.5
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
VI
Enable Control Pin DC Input Voltage
−0.5 to +5.5
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
ICC
DC Supply Current Through VCC
$100
mA
IL
DC Supply Current Through VL
$100
mA
IGND
DC Ground Current Through Ground Pin
$100
mA
TSTG
Storage Temperature
−65 to +150
°C
400
7000
2000
100
V
V
V
mA
ESD Rating
Machine Model
Human Body Model
Charged Device Model
LU Pass
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
High−side Positive DC Supply Voltage
0.9
4.5
V
VL
Low−side Positive DC Supply Voltage
0.9
4.5
V
VI
Enable Control Pin Voltage
GND
4.5
V
VIO
Bus Input/Output Voltage
GND
GND
4.5
4.5
V
TA
Operating Temperature Range
−55
+125
°C
0
10
ns
Dt/DV
I/O VCC
I/O VL
Input Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
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4
NLSX5014
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Max
Min
Max
Unit
VCC (V)
(Note 2)
VL (V)
(Note 3)
I/O VCC Input HIGH Voltage
0.9 – 4.5
0.9 – 4.5
2/3 *
VCC
−
−
2/3 *
VCC
−
V
VILC
I/O VCC Input LOW Voltage
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VCC
−
1/3 *
VCC
V
VIHL
I/O VL Input HIGH Voltage
0.9 – 4.5
0.9 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
VILL
I/O VL Input LOW Voltage
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
VIH
Control Pin Input HIGH Voltage
TA = +25°C
1.2 – 4.5
1.2 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
VIL
Control Pin Input LOW Voltage
TA = +25°C
1.2 – 4.5
1.2 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
VIH
Control Pin Input HIGH Voltage
TA = +25°C
VCC < 1.2
VL < 1.2
VL
−
−
VL
−
V
VIL
Control Pin Input LOW Voltage
TA = +25°C
VCC < 1.2
VL < 1.2
−
−
0
−
0
V
VOHC
I/O VCC Output HIGH Voltage
I/O VCC source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VCC
−
−
0.9 *
VCC
−
V
VOLC
I/O VCC Output LOW Voltage
I/O VCC sink
current = 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
VOHL
I/O VL Output HIGH Voltage
I/O VL source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VL
−
−
0.9 * VL
−
V
VOLL
I/O VL Output LOW Voltage
I/O VL sink current
= 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
IQVCC
VCC Supply Current
EN = VL, IO = 0 A,
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
TA = +25°C,
EN = 0 V
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
0.9 – 4.5
0.9 – 4.5
−
−
0.5
−
1.5
mA
0.9 – 4.5
0.9 – 4.5
−
−
0.5
−
1.5
mA
Symbol
Parameter
VIHC
IQVL
ITS−VCC
VL Supply Current
VCC Tristate Output Mode
Supply Current
Test Conditions
(Note 1)
−555C to +1255C
Typ
(Note 4)
Min
ITS−VL
VL Tristate Output Mode
Supply Current
IOZ
I/O Tristate Output Mode
Leakage Current
TA = +25°C,
EN = 0V
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1.5
mA
II
Control Pin Input Current
TA = +25°C
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1
mA
I/O VCC = 0 to 4.5V,
0
0
−
−
1
−
1.5
mA
I/O VL = 0 to 4.5 V
0.9 – 4.5
0
−
−
1
−
1.5
0
0.9 – 4.5
−
−
1
−
1.5
IOFF
Power Off Leakage Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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5
NLSX5014
TIMING CHARACTERISTICS
−555C to +1255C
Symbol
Parameter
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
Min
Typ
(Note 8)
Max
Unit
0.9 – 4.5
0.9 – 4.5
−
−
8.5
nS
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
tR−VCC
I/O VCC Rise Time
CIOVCC = 15 pF
tF−VCC
I/O VCC Fall Time
CIOVCC = 15 pF
tR−VL
tF−VL
ZOVCC
ZOVL
I/O VL Rise Time
I/O VL Fall Time
CIOVL = 15 pF
CIOVL = 15 pF
nS
nS
nS
I/O VCC One−Shot
Output Impedance
(Note 9)
0.9
1.8
4.5
0.9 – 4.5
−
−
−
37
20
6.0
−
−
−
W
I/O VL One−Shot Output Impedance
(Note 9)
0.9
1.8
4.5
0.9 – 4.5
−
−
−
37
20
6.0
−
−
−
W
CIOVCC = 15 pF
0.9 – 4.5
0.9 – 4.5
−
−
35
nS
1.8 – 4.5
1.8 – 4.5
−
−
10
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
1.0 – 4.5
1.0 – 4.5
−
−
37
1.8 – 4.5
1.8 – 4.5
−
−
11
1.2 – 4.5
1.2 – 4.5
−
−
40
1.8 – 4.5
1.8 – 4.5
−
−
13
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
1.0 – 4.5
1.0 – 4.5
−
−
37
1.8 – 4.5
1.8 – 4.5
−
−
11
1.2 – 4.5
1.2 – 4.5
−
−
40
1.8 – 4.5
1.8 – 4.5
−
−
13
tPD_VL−VCC Propagation Delay
(Driving I/O VCC)
CIOVCC = 30 pF
CIOVCC = 50 pF
CIOVCC = 100 pF
tPD_VCC−VL Propagation Delay
(Driving I/O VL)
CIOVL = 15 pF
CIOVL = 30 pF
CIOVL = 50 pF
CIOVL = 100 pF
nS
tSK
Channel−to−Channel
Skew
CIOVCC = 15 pF, CIOVL = 15 pF
(Note 9)
0.9 – 4.5
0.9 – 4.5
−
−
0.15
nS
IIN_PEAK
Input Driver Maximum
Peak Current
EN = VL;
I/O_VCC = 1 MHz Square Wave,
Amplitude = VCC, or
I/O_VL = 1 MHz Square Wave,
Amplitude = VL (Note 9)
0.9 – 4.5
0.9 – 4.5
−
−
5.0
mA
5.
6.
7.
8.
Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
9. Guaranteed by design.
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6
NLSX5014
TIMING CHARACTERISTICS (continued)
−555C to +1255C
Symbol
tEN−VCC
tEN−VL
I/O_VCC Output Enable Time
I/O_VL Output Enable Time
tDIS−VCC I/O_VCC Output Disable Time
tDIS−VL
MDR
Test Conditions
(Note 10)
VCC (V)
(Note 11)
VL (V)
(Note 12)
Min
Typ
(Note 13)
Max
Unit
tPZH
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
160
nS
tPZL
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPZH
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
160
tPZL
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPHZ
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
tPHZ
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
CIO = 15 pF
0.9 – 4.5
0.9 – 4.5
50
−
−
1.8 – 4.5
1.8 – 4.5
140
−
−
0.9 – 4.5
0.9 – 4.5
40
−
−
1.8 – 4.5
1.8 – 4.5
120
−
−
1.0 – 4.5
1.0 – 4.5
30
−
−
1.8 – 4.5
1.8 – 4.5
100
−
−
1.2 – 4.5
1.2 – 4.5
20
−
−
1.8 – 4.5
1.8 – 4.5
60
−
−
Parameter
I/O_VL Output Disable Time
Maximum Data Rate
CIO = 30 pF
CIO = 50 pF
CIO = 100 pF
nS
nS
nS
mbps
10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
13. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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NLSX5014
DYNAMIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
CPD_VCC
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
Test Conditions
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
VCC (V)
(Note 14)
VL (V)
(Note 15)
Typ
(Note 16)
Unit
0.9
4.5
39
pF
1.5
1.8
20
1.8
1.5
17
1.8
1.8
14
1.8
2.8
13
2.5
2.5
14
2.8
1.8
13
4.5
0.9
19
0.9
4.5
37
1.5
1.8
30
1.8
1.5
29
1.8
1.8
29
1.8
2.8
29
2.5
2.5
30
2.8
1.8
29
4.5
0.9
19
0.9
4.5
29
1.5
1.8
29
1.8
1.5
29
1.8
1.8
29
1.8
2.8
29
2.5
2.5
30
2.8
1.8
29
4.5
0.9
35
0.9
4.5
21
1.5
1.8
18
1.8
1.5
18
1.8
1.8
14
1.8
2.8
13
2.5
2.5
14
2.8
1.8
13
4.5
0.9
30
pF
pF
pF
14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
16. Typical values are at TA = +25°C.
17. CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the
VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC
+ ICC VL and NSW = total number of outputs switching.
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NLSX5014
STATIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
CPD_VCC
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
Test Conditions
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
VCC (V)
(Note 18)
VL (V)
(Note 19)
Typ
(Note 20)
Unit
0.9
4.5
0.01
pF
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
20. Typical values are at TA = +25°C
www.onsemi.com
9
pF
pF
pF
NLSX5014
NLSX5014
VL
VCC
NLSX5014
VL
EN
I/O VL
Source
VCC
EN
I/O VL
I/O VCC
I/O VCC
CIOVL
CIOVCC
Source
tRISE/FALL v
3 ns
I/O VL
90%
50%
10%
I/O VCC
tRISE/FALL v 3 ns
90%
50%
10%
tPD_VL−VCC
I/O VCC
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 3. Driving I/O VL Test Circuit and Timing
tR−VL
Figure 4. Driving I/O VCC Test Circuit and Timing
VCC
PULSE
GENERATOR
2xVCC
OPEN
R1
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 5. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
90%
50%
10%
tR
EN
VCC
90%
50%
10%
tPHL
GND
VL
50%
tPZL
Output
50%
tPZH
tF
Output
50%
GND
tPLZ
tPHZ
HIGH
IMPEDANCE
10%
VOL
90%
VOH
Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement
www.onsemi.com
10
HIGH
IMPEDANCE
NLSX5014
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
VL pins to a high impedance state. Normal translation
operation occurs when the EN pin is equal to a logic high
signal. The EN pin is referenced to the VL supply and has
Over−Voltage Tolerant (OVT) protection.
The NLSX5014 auto−sense translator provides
bi−directional logic voltage level shifting to transfer data
in multiple supply voltage systems. These level translators
have two supply voltages, VL and VCC, which set the logic
levels on the input and output sides of the translator. When
used to transfer data from the I/O VL to the I/O VCC ports,
input signals referenced to the VL supply are translated to
output signals with a logic level matched to VCC. In a
similar manner, the I/O VCC to I/O VL translation shifts
input signals with a logic level compatible to VCC to an
output signal matched to VL.
The NLSX5014 translator consists of bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. One−shot
circuits are used to detect the rising or falling input signals.
In addition, the one−shots decrease the rise and fall times
of the output signal for high−to−low and low−to−high
transitions.
Uni−Directional versus Bi−Directional Translation
The NLSX5014 translator can function as a
non−inverting uni−directional translator. One advantage of
using the translator as a uni−directional device is that each
I/O pin can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
The values of the VL and VCC supplies can be set to
anywhere between 0.9 and 4.5 V. Design flexibility is
maximized because VL may be either greater than or less
than the VCC supply. In contrast, the majority of the
competitive auto sense translators has a restriction that the
value of the VL supply must be equal to less than (VCC −
0.4) V.
The sequencing of the power supplies will not damage
the device during power−up operation. In addition, the I/O
VCC and I/O VL pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 to 0.1 mF decoupling capacitors should
be used on the VL and VCC power supply pins. Ceramic
capacitors are a good design choice to filter and bypass any
noise signals on the voltage lines to the ground plane of the
PCB. The noise immunity will be maximized by placing
the capacitors as close as possible to the supply and ground
pins, along with minimizing the PCB connection traces.
The NLSX5014 translators have a power down feature
that provides design flexibility. The output ports are
disabled when either power supply is off (VL or VCC = 0 V).
This feature causes all of the I/O pins to be in the power
saving high impedance state.
Input Driver Requirements
Auto−sense translators such as the NLSX5014 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent in the opposite direction. For
proper operation, the input driver to the auto−sense
translator should be capable of driving 2 mA of peak output
current. The bi−directional configuration of the translator
results in both input stages being active for a very short time
period. Although the peak current from the input signal
circuit is relatively large, the average current is small and
consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5014 translator has an Enable pin (EN) that
provides tri−state operation at the I/O pins. Driving the
Enable pin to a low logic level minimizes the power
consumption of the device and drives the I/O VCC and I/O
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P
CASE 523AE−01
ISSUE A
DATE 11 JUN 2007
1
SCALE 4:1
A B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN 1 REFERENCE
2X
0.10 C
2X
0.10 C
L1
DETAIL A
E
NOTE 5
TOP VIEW
DETAIL B
A
0.05 C
12X
0.05 C
A1
A3
8X
C
SIDE VIEW
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
K
L
L1
L2
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.70 BSC
2.00 BSC
0.40 BSC
0.20
---0.45
0.55
0.00
0.03
0.15 REF
K
5
GENERIC
MARKING DIAGRAM*
7
DETAIL A
e
1
12X
DETAIL B
OPTIONAL
CONSTRUCTION
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH 0.03
MAX ON BOTTOM SURFACE OF
TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
11
L
L2
12X
XXM
G
b
0.10
M
C A B
0.05
M
C
BOTTOM VIEW
NOTE 3
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
2.00
1
0.40
PITCH
0.32
2.30
11X
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON23418D
UQFN12 1.7 X 2.0, 0.4P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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