DATA SHEET
www.onsemi.com
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
SOIC−16
D SUFFIX
CASE 751B
MC14504B
The MC14504B is a hex non−inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC.
The VCC level sets the input signal levels while VDD selects the output
voltage levels.
PIN ASSIGNMENT
Features
UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for VDD and VCC
Diode Protected Inputs to VSS
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Value
Unit
VCC
DC Supply Voltage Range
−0.5 to +18.0
V
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin
Input Voltage Range
(DC or Transient)
−0.5 to +18.0
V
Vout
Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
C
Tstg
Storage Temperature Range
−65 to +150
C
TL
Lead Temperature
(8−Second Soldering)
260
C
Iin, Iout
Parameter
TSSOP−16
DT SUFFIX
CASE 948F
VCC
1
16
VDD
Aout
2
15
Fout
Ain
3
14
Fin
Bout
4
13
MODE
Bin
5
12
Eout
Cout
6
11
Ein
Cin
7
10
Dout
VSS
8
9
Din
MARKING DIAGRAMS
16
16
14504BG
AWLYWW
1
14
504B
ALYWG
G
1
SOIC−16
A
WL, L
Y
WW, W
G or G
TSSOP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Semiconductor Components Industries, LLC, 2014
December, 2022 − Rev. 10
1
Publication Order Number:
MC14504B/D
MC14504B
LOGIC DIAGRAM
VCC
VDD
LEVEL
SHIFTER
INPUT
OUTPUT
TTL/CMOS
MODE SELECT
MODE
Mode Select
Input Logic
Levels
Output Logic
Levels
1 (VCC)
TTL
CMOS
0 (VSS)
CMOS
CMOS
1/6 of package shown.
ORDERING INFORMATION
Package
Shipping†
MC14504BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14504BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC14504BDTG
TSSOP−16
(Pb−Free)
96 Units / Rail
MC14504BDTR2G
TSSOP−16
(Pb−Free)
2500 Units / Tape & Reel
Device
NLV14504BDR2G*
NLV14504BDTR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14504B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
125_C
VCC
Vdc
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
VOL
−
−
−
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
−
−
−
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
5.0
5.0
5.0
10
10
15
10
15
15
−
−
−
−
−
0.8
0.8
1.5
1.5
3.0
−
−
−
−
−
1.3
1.3
2.25
2.25
4.5
0.8
0.8
1.5
1.5
3.0
−
−
−
−
−
0.8
0.8
1.4
1.5
2.9
5.0
5.0
5.0
5.0
10
10
15
10
15
15
2.0
2.0
3.6
3.6
7.1
−
−
−
−
−
2.0
2.0
3.5
3.5
7.0
1.5
1.5
2.75
2.75
5.5
−
−
−
−
−
2.0
2.0
3.5
3.5
7.0
−
−
−
−
−
−
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
−
−
−
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
−
15
−
0.1
−
0.00001
0.1
−
1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
−
5.0
7.5
−
−
pF
IDD or
ICC
−
−
−
5.0
10
15
−
−
−
0.05
0.10
0.20
−
−
−
0.0005
0.0010
0.0015
0.05
0.10
0.20
−
−
−
1.5
3.0
6.0
mAdc
Quiescent Current
(Per Package)
TTL−CMOS Mode
IDD
5.0
5.0
5.0
5.0
10
15
−
−
−
0.5
1.0
2.0
−
−
−
0.0005
0.0010
0.0015
0.5
1.0
2.0
−
−
−
3.8
7.5
15
mAdc
Quiescent Current
(Per Package)
TTL−CMOS Mode
ICC
5.0
5.0
5.0
5.0
10
15
−
−
−
5.0
5.0
5.0
−
−
−
2.5
2.5
2.5
5.0
5.0
5.0
−
−
−
6.0
6.0
6.0
mAdc
Symbol
Characteristic
Output Voltage
Vin = 0 V
Vin = VCC
“0” Level
“1” Level
Input Voltage
“0” Level
(VOL = 1.0 Vdc) TTL−CMOS
(VOL = 1.5 Vdc) TTL−CMOS
(VOL = 1.0 Vdc) CMOS−CMOS
(VOL = 1.5 Vdc) CMOS−CMOS
(VOL = 1.5 Vdc) CMOS−CMOS
VIL
Input Voltage
“1” Level
(VOH = 9.0 Vdc) TTL−CMOS
(VOH = 13.5 Vdc) TTL−CMOS
(VOH = 9.0 Vdc) CMOS−CMOS
(VOH = 13.5 Vdc) CMOS−CMOS
(VOH = 13.5 Vdc) CMOS−CMOS
VIH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Quiescent Current
(Per Package)
CMOS−CMOS Mode
Source
Sink
Vdc
Vdc
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
www.onsemi.com
3
MC14504B
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Propagation Delay, High to Low
Propagation Delay, Low to High
Output Rise and Fall Time
Symbol
tPHL
VCC
Vdc
5.0
5.0
VDD
Vdc
10
15
Min
−
−
CMOS – CMOS
VDD > VCC
5.0
5.0
10
10
15
15
CMOS – CMOS
VCC > VDD
10
15
15
TTL – CMOS
VDD > VCC
Limits
Typ
(Note 3)
140
140
Max
280
280
−
−
−
120
120
70
240
240
140
5.0
5.0
10
−
−
−
185
185
175
370
370
350
5.0
5.0
10
15
−
−
170
160
340
320
CMOS – CMOS
VDD > VCC
5.0
5.0
10
10
15
15
−
−
−
170
170
100
340
340
200
CMOS – CMOS
VCC > VDD
10
15
15
5.0
5.0
10
−
−
−
275
275
145
550
550
290
ALL
−
−
−
5.0
10
15
−
−
−
100
50
40
200
100
80
Shifting Mode
TTL – CMOS
VDD > VCC
tPLH
tTLH, tTHL
Unit
ns
ns
ns
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
7
6
VCC = 10 V
5
4
3
VCC = 5 V
2
1
6
5
4
3
2
1
0
0
0
5
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
0
Figure 1. Input Switchpoint CMOS to CMOS Mode
10
5
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
20
VDD, SUPPLY VOLTAGE (Vdc)
15
5
Figure 2. Input Switchpoint TTL to CMOS Mode
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
20
VDD, SUPPLY VOLTAGE (Vdc)
VCC = 5 V
15
10
0
5
0
0
5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
0
Figure 3. Operating Boundary CMOS to CMOS Mode
5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 4. Operating Boundary TTL to CMOS Mode
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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