NLV14511BDWR2G

DATA SHEET www.onsemi.com BCD-to-Seven Segment Latch/Decoder/Driver SOIC−16 D SUFFIX CASE 751B MC14511B The MC14511B BCD−to−seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4−bit storage latch, an 8421 BCD−to−seven segment decoder, and an output drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are used to test the display, to turn−off or pulse modulate the brightness of the display, and to store a BCD code, respectively. It can be used with seven−segment light−emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly. Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. Features • • • • • • • • • • • • • • Low Logic Circuit Power Dissipation High−Current Sourcing Outputs (Up to 25 mA) Latch Storage of Code Blanking Input Lamp Test Provision Readout Blanking on all Illegal Input Combinations Lamp Intensity Modulation Capability Time Share (Multiplexing) Facility Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low−power TTL Loads, One Low−power Schottky TTL Load, or Two HTL Loads Over the Rated Temperature Range Chip Complexity: 216 FETs or 54 Equivalent Gates Triple Diode Protection on all Inputs NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant SO−16 WB DW SUFFIX CASE 751G MARKING DIAGRAMS 16 14511B AWLYYWWG 16 14511BG AWLYWW 1 1 SOIC−16 A WL, L YY, Y WW, W G SO−16 WB = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1) Parameter Symbol Value Unit −0.5 to +18.0 V VDD DC Supply Voltage Range Vin Input Voltage Range, All Inputs −0.5 to VDD + 0.5 V I DC Current Drain per Input Pin 10 mA PD Power Dissipation, per Package (Note 2) 500 mW TA Operating Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C IOHmax Maximum Output Drive Current (Source) per Output 25 mA POHmax Maximum Continuous Output Power (Source) per Output (Note 3) 50 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: “D/DW” Packages: –7.0 mW/°C From 65°C to 125°C 3. POHmax = IOH (VDD − VOH) © Semiconductor Components Industries, LLC, 2014 March, 2022 − Rev. 13 1 Publication Order Number: MC14511B/D MC14511B Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high−impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. PIN ASSIGNMENT B 1 16 VDD C 2 15 f LT 3 14 g BI 4 13 a LE 5 12 b D 6 11 c A 7 10 d VSS 8 9 e a f g e b c d DISPLAY 0 1 2 3 4 5 6 7 8 9 TRUTH TABLE LE BI LT X X 0 X 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 Inputs D C X X X X 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X B X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X a 1 0 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 b 1 0 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 c 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 d 1 0 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 * Outputs e f 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 X = Don’t Care *  Depends upon the BCD code previously applied when LE = 0 www.onsemi.com 2 g 1 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Display 8 Blank 0 1 2 3 4 5 6 7 8 9 Blank Blank Blank Blank Blank Blank * MC14511B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55°C 25°C VDD 125°C Symbol Vdc Min Max Min Typ (Note 4) “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.1 9.1 14.1 − − − 4.1 9.1 14.1 4.57 9.58 14.59 − − − 4.1 9.1 14.1 − − − Vdc Input Voltage # “0” Level (VO = 3.8 or 0.5 Vdc) (VO = 8.8 or 1.0 Vdc) (VO = 13.8 or 1.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 4.1 − 3.9 − 3.4 − − − − − − − 4.1 − 3.9 − 3.4 − 4.57 4.24 4.12 3.94 3.70 3.54 − − − − − − 4.1 − 3.5 − 3.0 − − − − − − − 10 9.1 − 9.0 − 8.6 − − − − − − − 9.1 − 9.0 − 8.6 − 9.58 9.26 9.17 9.04 8.90 8.70 − − − − − − 9.1 − 8.6 − 8.2 − − − − − − − Vdc 15 14.1 − 14 − 13.6 − − − − − − − 14.1 − 14 − 13.6 − 14.59 14.27 14.18 14.07 13.95 13.70 − − − − − − 14.1 − 13.6 − 13.2 − − − − − − − Vdc 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 Characteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD (VO = 0.5 or 3.8 Vdc) (VO = 1.0 or 8.8 Vdc) (VO = 1.5 or 13.8 Vdc) Output Drive Voltage (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) Source VOH (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) Output Drive Current (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Sink Input Current IOL Iin Max Min Max Unit Vdc Vdc Vdc mAdc mAdc Input Capacitance Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 mA IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Total Supply Current (Notes 5 & 6) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (1.9 mA/kHz) f + IDD IT = (3.8 mA/kHz) f + IDD IT = (5.7 mA/kHz) f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Noise immunity specified for worst−case input combination. Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc 5. The formulas given are for the typical characteristics only at 25°C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in mA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency. www.onsemi.com 3 MC14511B SWITCHING CHARACTERISTICS (Note 7) (CL = 50 pF, TA = 25°C) VDD Vdc Min Typ Max 5.0 10 15 − − − 40 30 25 80 60 50 5.0 10 15 − − − 125 75 65 250 150 130 5.0 10 15 − − − 640 250 175 1280 500 350 5.0 10 15 − − − 720 290 200 1440 580 400 5.0 10 15 − − − 600 200 150 750 300 220 5.0 10 15 − − − 485 200 160 970 400 320 5.0 10 15 − − − 313 125 90 625 250 180 tPHL 5.0 10 15 − − − 313 125 90 625 250 180 Setup Time tsu 5.0 10 15 100 40 30 − − − − − − ns Hold Time th 5.0 10 15 60 40 30 − − − − − − ns tWL 5.0 10 15 520 220 130 260 110 65 − − − ns Symbol Characteristic Output Rise Time tTLH = (0.40 ns/pF) CL + 20 ns tTLH = (0.25 ns/pF) CL + 17.5 ns tTLH = (0.20 ns/pF) CL + 15 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 50 ns tTHL = (0.75 ns/pF) CL + 37.5 ns tTHL = (0.55 ns/pF) CL + 37.5 ns tTHL Data Propagation Delay Time tPLH = (0.40 ns/pF) CL + 620 ns tPLH = (0.25 ns/pF) CL + 237.5 ns tPLH = (0.20 ns/pF) CL + 165 ns tPHL = (1.3 ns/pF) CL + 655 ns tPHL = (0.60 ns/pF) CL + 260 ns tPHL = (0.35 ns/pF) CL + 182.5 ns tPLH Blank Propagation Delay Time tPLH = (0.30 ns/pF) CL + 585 ns tPLH = (0.25 ns/pF) CL + 187.5 ns tPLH = (0.15 ns/pF) CL + 142.5 ns tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL = (0.45 ns/pF) CL + 177.5 ns tPHL = (0.35 ns/pF) CL + 142.5 ns tPLH Lamp Test Propagation Delay Time tPLH = (0.45 ns/pF) CL + 290.5 ns tPLH = (0.25 ns/pF) CL + 112.5 ns tPLH = (0.20 ns/pF) CL + 80 ns tPHL = (1.3 ns/pF) CL + 248 ns tPHL = (0.45 ns/pF) CL + 102.5 ns tPHL = (0.35 ns/pF) CL + 72.5 ns tPLH tPHL tPHL Latch Enable Pulse Width 7. The formulas given are for the typical characteristics only. www.onsemi.com 4 Unit ns ns ns ns ns MC14511B Input LE low, and Inputs D, BI and LT high. f in respect to a system clock. All outputs connected to respective CL loads. 20 ns 20 ns 90% 50% 1 2f A, B, AND C VDD 10% VSS 50% DUTY CYCLE VOH 50% ANY OUTPUT VOL Figure 1. Dynamic Power Dissipation Signal Waveforms 20 ns 20 ns 20 ns VDD 90% 50% 10% INPUT C 10% th VDD VOH 90% INPUT C 50% 50% OUTPUT g VSS tsu VSS tPHL tPLH LE VDD 90% 50% VSS 10% VOL VOH OUTPUT g tTHL tTLH VOL (b) Input D low, Inputs A, B, BI and LT high. (a) Inputs D and LE low, and Inputs A, B, BI and LT high. 20 ns 20 ns LE VDD 90% 50% 10% tWL (c) Data DCBA strobed into latches. Figure 2. Dynamic Signal Waveforms www.onsemi.com 5 VSS MC14511B CONNECTIONS TO VARIOUS DISPLAY READOUTS LIGHT EMITTING DIODE (LED) READOUT VDD VDD COMMON ANODE LED COMMON CATHODE LED ≈ 1.7 V ≈ 1.7 V VSS VSS INCANDESCENT READOUT VDD FLUORESCENT READOUT VDD VDD ** DIRECT (LOW BRIGHTNESS) FILAMENT SUPPLY VSS VSS VSS OR APPROPRIATE VOLTAGE BELOW VSS. (CAUTION: Maximum working voltage = 18.0 V) GAS DISCHARGE READOUT VDD LIQUID CRYSTAL (LCD) READOUT APPROPRIATE VOLTAGE EXCITATION (SQUARE WAVE, VSS TO VDD) VDD 1/4 OF MC14070B VSS VSS ** A filament pre−warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. Direct DC drive of LCD’s not recommended for life of LCD readouts. www.onsemi.com 6 MC14511B BI4 13a A7 12b 11c B1 10d 9e 15f C2 14g LT3 D6 VDD = PIN 16 VSS = PIN 8 LE5 Figure 3. Logic Diagram ORDERING INFORMATION Package Shipping† MC14511BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14511BDR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC14511BDWR2G SO−16 WB (Pb−Free) 1000 / Tape & Reel NLV14511BDWR2G* SO−16 WB (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 WB CASE 751G ISSUE E 1 SCALE 1:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* 16 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42567B SOIC−16 WB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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