DATA SHEET
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Schmitt Trigger Buffer,
Dual, Non-Inverting
MARKING
DIAGRAMS
6
NL27WZ17
1
SC−88
DF SUFFIX
CASE 419B−02
The NL27WZ17 is a high performance dual buffer with
Schmitt−Trigger inputs operating from a 1.65 to 5.5 V supply.
Features
•
•
•
•
•
•
•
•
•
Designed for 1.65 V to 5.5 V VCC Operation
3.7 ns tPD at VCC = 5 V (Typ)
Inputs/Outputs Overvoltage Tolerant up to 5.5 V
IOFF Supports Partial Power Down Protection
Sink 32 mA at 4.5 V
Available in SC−88, SC−74, and UDFN6 Packages
Chip Complexity < 100 FETs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
XXXMG
G
1
6
1
1
SC−74
CASE 318F−05
XXX MG
G
1
UDFN6
1.45x1.0, 0.5P
CASE 517AQ
UDFN6
1x1, 0.35P
CASE 517BX
XM
XM
1
X, XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
A1
1
Y1
A2
1
Y2
*Date Code orientation and/or position may vary
depending upon manufacturing location.
ORDERING INFORMATION
Figure 1. Logic Symbol
© Semiconductor Components Industries, LLC, 2012
March, 2022 − Rev. 14
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1
Publication Order Number:
NL27WZ17/D
NL27WZ17
A1
A1
1
6
Y1
GND
2
5
VCC
A2
3
4
Y2
Y1
1
6
GND
2
5
VCC
A2
3
4
Y2
(SC−88/SC−74)
UDFN6
Figure 2. Pinout (Top View)
PIN ASSIGNMENT
FUNCTION TABLE
Pin
Function
1
A1
L
L
2
GND
H
H
3
A2
4
Y2
5
VCC
6
Y1
A Input
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2
Y Output
NL27WZ17
MAXIMUM RATINGS
Symbol
Characteristics
Value
Units
VCC
DC Supply Voltage
SC−88 (NLV)
SC−88, SC−74, UDFN6
−0.5 to +7.0
−0.5 to +6.5
V
VIN
DC Input Voltage
SC−88 (NLV)
SC−88, SC−74, UDFN6
−0.5 to +7.0
−0.5 to +6.5
V
VOUT
DC Output Voltage
SC−88 (NLV)
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC +0.5
−0.5 to +7.0
−0.5 to +7.0
V
DC Output Voltage
SC−88, SC−74, UDFN6
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC +0.5
−0.5 to +6.5
−0.5 to +6.5
V
IIK
DC Input Diode Current, VIN < GND
−50
mA
IOK
DC Output Diode Current, VOUT < GND
−50
mA
IOUT
DC Output Source/Sink Current
±50
mA
DC Supply Current per Supply Pin or Ground Pin
±100
mA
−65 to +150
°C
ICC or IGND
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 secs
260
°C
TJ
Junction Temperature under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
SC−88
SC−74
UDFN6
377
320
154
°C/W
PD
Power Dissipation in Still Air
SC−88
SC−74
UDFN6
332
390
812
mW
Level 1
−
UL 94−V−0 @ 0.125 in
−
Human Body Model
Charged Device Model
(NLV) Charged Device Model
2000
1000
N/A
V
(NLV)
±100
±500
mA
MSL
FR
VESD
ILATCHUP
Moisture Sensitivity
Flamebility Rating
Oxygen Index: 28 to 34
ESD Withstand Voltage (Note 3)
Latchup Performance (Note 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow per JESD51−7.
3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.
4. Tested to EIA/JESD78 Class II.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Positive DC Supply Voltage
VIN
DC Input Voltage
VOUT
TA
tr , tf
DC Output Voltage
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
Operating Temperature Range
Input Transition Rise or Fall Rate
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Min
Max
Unit
1.65
5.5
V
0
5.5
V
0
0
0
VCC
5.5
5.5
V
−55
+125
°C
0
0
0
0
No Limit
No Limit
No Limit
No Limit
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
NL27WZ17
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
VT+
Parameter
Condition
Positive Input
Threshold
Voltage (NLV)
Positive Input
Threshold
Voltage
VT−
Negative
Input
Threshold
Voltage (NLV)
Negative
Input
Threshold
Voltage
VH
VOH
VOL
Input
Hysteresis
Voltage
High−Level
Output
Voltage
VIN = VIH or
VIL
Low−Level
Output
Voltage
VIN = VIH or
VIL
−40°C 3 TA 3 85°C −55°C 3 TA 3 125°C
VCC (V)
Min
Typ
Max
Min
Max
Min
Max
Unit
1.65
0.6
1.0
1.4
0.6
1.4
0.6
1.4
V
2.3
1.0
1.5
1.8
1.0
1.8
1.0
1.8
2.7
1.2
1.7
2.0
1.2
2.0
1.2
2.0
3.0
1.3
1.9
2.2
1.3
2.2
1.3
2.2
4.5
1.9
2.7
3.1
1.9
3.1
1.9
3.1
5.5
2.2
3.3
3.6
2.2
3.6
2.2
3.6
1.65
−
1.0
1.4
−
1.4
−
1.4
2.3
−
1.5
1.8
−
1.8
−
1.8
2.7
−
1.7
2.0
−
2.0
−
2.0
3.0
−
1.9
2.2
−
2.2
−
2.2
4.5
−
2.7
3.1
−
3.1
−
3.1
5.5
−
3.3
3.6
−
3.6
−
3.6
1.65
0.2
0.5
0.8
0.2
0.8
0.2
0.8
2.3
0.4
0.75
1.15
0.4
1.15
0.4
1.15
2.7
0.5
0.87
1.4
0.5
1.4
0.5
1.4
3.0
0.6
1.0
1.5
0.6
1.5
0.6
1.5
4.5
1.0
1.5
2.0
1.0
2.0
1.0
2.0
5.5
1.2
1.9
2.3
1.2
2.3
1.2
2.3
1.65
0.2
0.5
−
0.2
−
0.2
−
2.3
0.4
0.75
−
0.4
−
0.4
−
2.7
0.5
0.87
−
0.5
−
0.5
−
3.0
0.6
1.0
−
0.6
−
0.6
−
4.5
1.0
1.5
−
1.0
−
1.0
−
5.5
1.2
1.9
−
1.2
−
1.2
−
1.65
0.1
0.48
0.9
0.1
0.9
0.1
0.9
2.3
0.25
0.75
1.1
0.25
1.1
0.25
1.1
2.7
0.3
0.83
1.15
0.3
1.15
0.3
1.15
3
0.4
0.93
1.2
0.4
1.2
0.4
1.2
4.5
0.6
1.2
1.5
0.6
1.5
0.6
1.5
5.5
0.7
1.4
1.7
0.7
1.7
0.7
1.7
1.65 to 5.5
VCC − 0.1
VCC
−
VCC − 0.1
−
VCC − 0.1
−
IOH = −4 mA
1.65
1.29
1.52
−
1.29
−
1.29
−
IOH = −8 mA
2.3
1.9
2.1
−
1.9
−
1.9
−
IOH = −12 mA
2.7
2.2
2.4
−
2.2
−
2.2
−
IOH = −16 mA
3
2.4
2.7
−
2.4
−
2.4
−
IOH = −24 mA
3
2.3
2.5
−
2.3
−
2.3
−
IOH = −32 mA
4.5
3.8
4
−
3.8
−
3.8
−
IOL = 100 mA
IOH = −100 mA
1.65 to 5.5
−
−
0.1
−
0.1
−
0.1
IOL = 4 mA
1.65
−
0.08
0.24
−
0.24
−
0.24
IOL = 8 mA
2.3
−
0.2
0.3
−
0.3
−
0.3
IOL = 12 mA
2.7
−
0.22
0.4
−
0.4
−
0.4
IOL = 16 mA
3
−
0.28
0.4
−
0.4
−
0.4
IOL = 24 mA
3
−
0.38
0.55
−
0.55
−
0.55
IOL = 32 mA
4.5
−
0.42
0.55
−
0.55
−
0.55
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4
V
V
V
V
V
V
NL27WZ17
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
−40°C 3 TA 3 85°C −55°C 3 TA 3 125°C
Symbol
Parameter
Condition
VCC (V)
Min
Typ
Max
Min
Max
Min
Max
Unit
IIN
Input Leakage
Current
VIN = 5.5 V or
GND
1.65 to 5.5
−
−
±0.1
−
±1.0
−
±1.0
mA
IOFF
Power Off
Leakage
Current
VIN = 5.5 V or
VOUT = 5.5 V
0
−
−
1
−
10
−
10
mA
ICC
Quiescent
Supply
Current
VIN = 5.5 V or
GND
5.5
−
−
1
−
10
−
10
mA
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Propagation
Delay, A to Y
(Figures 3 and 4)
−40°C 3 TA 3 85°C
−55°C 3 TA 3 125°C
VCC (V)
Min
Typ
Max
Min
Max
Min
Max
Unit
RL = 1 MW,
CL = 15 pF
1.65 to 1.95
−
9.1
15
−
15.6
−
15.6
ns
RL = 1 MW,
CL = 15 pF
2.3 to 2.7
−
5.0
9.0
−
9.5
−
9.5
3.0 to 3.6
−
3.7
6.3
−
6.5
−
6.5
4.5 to 5.5
−
3.1
5.2
−
5.5
−
5.5
3.0 to 3.6
−
4.4
7.2
−
7.5
−
7.5
4.5 to 5.5
−
3.7
5.9
−
6.2
−
6.2
Condition
RL = 500 W,
CL = 50 pF
CAPACITIVE CHARACTERISTICS
Symbol
CIN
Parameter
Condition
Typical
Unit
Input Capacitance
VCC = 5.5 V, VI = 0 V or VCC
2.5
pF
COUT
Output Capacitance
VCC = 5.5 V, VI = 0 V or VCC
4.0
pF
CPD
Power Dissipation Capacitance (Note 5)
10 MHz, VCC = 3.3 V, VIN = 0 V or VCC
10 MHz, VCC = 5.0 V, VIN = 0 V or VCC
11
12.5
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD · VCC · fin ) ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD · VCC2 · fin ) ICC · VCC.
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5
NL27WZ17
OPEN
2 x VCC
Test
Switch
Position
tPLH / tPHL
Open
tPLZ / tPZL
2 x VCC
tPHZ / tPZH
GND
GND
R1
RL
RT
RL, W
R1 , W
See AC Characteristics Table
−
−
−
See AC Characteristics Table
OUTPUT
DUT
CL, pF
CL *
−
−
−
See AC Characteristics Table
X = Don’t Care
CL includes probe and jig capacitance
RT is ZOUT of pulse generator (typically 50 W)
f = 1 MHz
Figure 3. Test Circuit
tr = 3 ns
tf = 3 ns
90%
90%
Vmi
INPUT
Vmi
INPUT
Vmi
10%
10%
tPHL
Vmi
GND
GND
tPZL
tPLH
Vmo
OUTPUT
VCC
VCC
tPLZ
~VCC
VOH
Vmo
OUTPUT
Vmo
VOL + VY
VOL
VOL
tPLH
OUTPUT
tPHL
Vmo
tPZH
VOH
Vmo
tPHZ
VOH
VOH − VY
Vmo
OUTPUT
VOL
~0 V
Figure 4. Switching Waveforms
Vmo, V
VCC, V
Vmi, V
tPLH, tPHL
1.65 to 1.95
VCC/2
VCC / 2
VCC / 2
0.15
2.3 to 2.7
VCC/2
VCC / 2
VCC / 2
0.15
3.0 to 3.6
VCC/2
VCC / 2
VCC / 2
0.3
4.5 to 5.5
VCC/2
VCC / 2
VCC / 2
0.3
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6
tPZL, tPLZ, tPZH, tPHZ
VY, V
NL27WZ17
ORDERING INFORMATION
Package
Specific Device Code
Pin1 Orientation
(See below)
Shipping†
NL27WZ17DFT2G
SC−88
MX
Q4
3000 / Tape & Reel
NL27WZ17DFT2G−L22348**
SC−88
MX
Q4
3000 / Tape & Reel
NLV27WZ17DFT2G*
SC−88
MX
Q4
3000 / Tape & Reel
NL27WZ17DBVT1G
SC−74
AC
Q4
3000 / Tape & Reel
NL27WZ17MU1TCG
UDFN6 1.45 x 1.0, 0.5P
K (Rotated 90° CW)
Q4
3000 / Tape & Reel
NL27WZ17MU3TCG
UDFN6 1.0 x 1.0, 0.35P
D
Q4
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**Please refer to NLV specifications for this device.
Pin 1 Orientation in Tape and Reel
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−74
CASE 318F
ISSUE P
6
1
SCALE 2:1
DATE 07 OCT 2021
GENERIC
MARKING DIAGRAM*
XXX MG
G
XXX
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 1:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. ANODE
6. CATHODE
STYLE 2:
PIN 1. NO CONNECTION
2. COLLECTOR
3. EMITTER
4. NO CONNECTION
5. COLLECTOR
6. BASE
STYLE 3:
PIN 1. EMITTER 1
2. BASE 1
3. COLLECTOR 2
4. EMITTER 2
5. BASE 2
6. COLLECTOR 1
STYLE 4:
PIN 1. COLLECTOR 2
2. EMITTER 1/EMITTER 2
3. COLLECTOR 1
4. EMITTER 3
5. BASE 1/BASE 2/COLLECTOR 3
6. BASE 3
STYLE 5:
PIN 1. CHANNEL 1
2. ANODE
3. CHANNEL 2
4. CHANNEL 3
5. CATHODE
6. CHANNEL 4
STYLE 7:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 8:
PIN 1. EMITTER 1
2. BASE 2
3. COLLECTOR 2
4. EMITTER 2
5. BASE 1
6. COLLECTOR 1
STYLE 9:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 10:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 11:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42973B
SC−74
STYLE 6:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6, 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
1
SCALE 4:1
A
B
D
DATE 15 MAY 2008
L
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
L1
PIN ONE
REFERENCE
0.10 C
ÉÉÉ
ÉÉÉ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
0.10 C
DETAIL B
MOLD CMPD
DETAIL B
0.05 C
6X
DIM
A
A1
A2
b
D
E
e
L
L1
OPTIONAL
CONSTRUCTIONS
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.07 REF
0.20
0.30
1.45 BSC
1.00 BSC
0.50 BSC
0.30
0.40
−−−
0.15
MOUNTING FOOTPRINT
0.05 C
A1
SIDE VIEW
A2
e
6X
C
SEATING
PLANE
6X
0.30
PACKAGE
OUTLINE
L
1.24
3
1
DETAIL A
6X
0.53
6
4
6X
BOTTOM VIEW
b
0.10 C A B
0.05 C
NOTE 3
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XM
X
M
= Specific Device Code
= Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30313E
UDFN6, 1.45x1.0, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6, 1x1, 0.35P
CASE 517BX
ISSUE O
SCALE 4:1
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
A B
D
ÉÉ
ÉÉ
ÉÉ
DATE 18 MAY 2011
E
DIM
A
A1
A3
b
D
E
e
L
L1
TOP VIEW
A3
0.05 C
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.12
0.22
1.00 BSC
1.00 BSC
0.35 BSC
0.25
0.35
0.30
0.40
0.05 C
SIDE VIEW
A1
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
5X
e
5X
0.48
L
6X
0.22
3
1
L1
1.18
6
4
6X
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
NOTE 3
0.53
1
PKG
OUTLINE
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XM
1
X = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56787E
UDFN6, 1x1, 0.35P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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