NLV74HC4053ADWRG

Analog Multiplexers/ Demultiplexers High−Performance Silicon−Gate CMOS MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4051A, HC4052A and HC4053A are identical in pinout to the metal−gate MC14051AB, MC14052AB and MC14053AB. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HC4852A. • • • • • SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F 1 QFN16 MN SUFFIX CASE 485AW MARKING DIAGRAMS 16 16 HC405xAG AWLYWW HC405xA AWLYWWG 1 Features • • • • • • SOIC−16 WIDE DW SUFFIX CASE 751G Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal−Gate Counterparts Low Noise In Compliance with the Requirements of JEDEC Standard No. 7A Chip Complexity: HC4051A − 184 FETs or 46 Equivalent Gates HC4052A − 168 FETs or 42 Equivalent Gates HC4053A − 156 FETs or 39 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS Compliant SOIC−16 1 SOIC−16 WIDE 16 HC40 5xA ALYWG G 1 4051 ALYWG G QFN16 TSSOP−16 x A WL, L YY, Y WW, W G or G = 1, 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. © Semiconductor Components Industries, LLC, 2017 July, 2021 − Rev. 12 1 Publication Order Number: MC74HC4051A/D MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE − MC74HC4051A LOGIC DIAGRAM MC74HC4051A Single−Pole, 8−Position Plus Common Off Control Inputs Enable C L L L L L L L L H L L L L H H H H X 13 X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 3 X COMMON OUTPUT/ INPUT Select B A L L H H L L H H X ON Channels L H L H L H L H X X0 X1 X2 X3 X4 X5 X6 X7 NONE X = Don’t Care Pinout: MC74HC4051A (Top View) VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9 1 X4 2 X6 3 X 4 X7 5 X5 6 7 Enable VEE 8 GND FUNCTION TABLE − MC74HC4052A LOGIC DIAGRAM MC74HC4052A Double−Pole, 4−Position Plus Common Off Control Inputs Enable B Select A L L L L H L L H H X L H L H X 12 ANALOG INPUTS/OUTPUTS CHANNEL‐SELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE X SWITCH 13 X COMMON OUTPUTS/INPUTS 1 5 2 Y SWITCH 3 X0 X1 X2 X3 NONE X = Don’t Care 4 6 Y0 Y1 Y2 Y3 Y Pinout: MC74HC4052A (Top View) 10 9 ON Channels PIN 16 = VCC PIN 7 = VEE PIN 8 = GND www.onsemi.com 2 VCC X2 X1 X X0 X3 A B 16 15 14 13 12 11 10 9 6 7 1 2 3 4 5 Y0 Y2 Y Y3 Y1 Enable VEE 8 GND MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE − MC74HC4053A Control Inputs LOGIC DIAGRAM MC74HC4053A Triple Single−Pole, Double−Position Plus Common Off 12 X0 13 X1 14 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 15 Y SWITCH 5 Z0 3 Z1 4 Z SWITCH Enable C L L L L L L L L H L L L L H H H H X X Y COMMON OUTPUTS/INPUTS Select B A L L H H L L H H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 L H L H L H L H X Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don’t Care Z 11 A 10 B 9 C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND CHANNEL‐SELECT INPUTS Pinout: MC74HC4053A (Top View) VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 6 7 NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch 1 2 3 4 5 Y1 Y0 Z1 Z Z0 Enable VEE 8 GND MAXIMUM RATINGS Symbol Parameter Unit –0.5 to +7.0 –0.5 to +14.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage (Referenced to GND) –7.0 to +5.0 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V ±25 mA 500 450 mW –65 to +150 _C I (Referenced to GND) (Referenced to VEE) Value DC Current, Into or Out of Any Pin PD Power Dissipation in Still Air, SOIC Package† TSSOP Package† Tstg Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C www.onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC4051A, MC74HC4052A, MC74HC4053A RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 2.0 6.0 12.0 V Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V –55 +125 _C 0 0 0 0 1000 600 500 400 ns VCC Positive DC Supply Voltage VEE (Referenced to GND) (Referenced to VEE) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Channel−Select or Enable Inputs Vin = VCC or GND, VEE = − 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VEE = GND VIS = VCC or GND; VIO = 0 V VEE = − 6.0 6.0 6.0 1 4 10 40 20 80 www.onsemi.com 4 mA MC74HC4051A, MC74HC4052A, MC74HC4053A DC CHARACTERISTICS — Analog Section Guaranteed Limit Symbol Ron VCC VEE −55 to 25°C Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 190 120 100 240 150 125 280 170 140 Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 150 100 80 190 125 100 230 140 115 Parameter Condition Maximum “ON” Resistance ≤85°C ≤125°C Unit W DRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 − 4.5 − 6.0 30 12 10 35 15 12 40 18 14 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3) 6.0 − 6.0 0.1 0.5 1.0 Maximum Off−ChannelHC4051A Vin = VIL or VIH; Leakage Current, HC4052A VIO = VCC − VEE; Common Channel HC4053A Switch Off (Figure 4) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On−ChannelHC4051A Vin = VIL or VIH; Leakage Current, HC4052A Switch−to−Switch = Channel−to−Channel HC4053A VCC − VEE; (Figure 5) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 mA Ion W mA AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) VCC V Guaranteed Limit −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figure 9) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Symbol Parameter Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: HC4051A HC4052A HC4053A 130 80 50 130 80 50 130 80 50 Feed−through 1.0 1.0 1.0 (All Switches Off) Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* HC4051A HC4052A HC4053A * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . www.onsemi.com 5 45 80 45 pF MC74HC4051A, MC74HC4052A, MC74HC4053A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW − − Parameter Condition Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 6) fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase fin Frequency Until dB Meter Reads −3dB; RL = 50W, CL = 10pF Off−Channel Feed−through Isolation (Figure 7) Feedthrough Noise. Channel−Select Input to Common I/O (Figure 8) − Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051A) THD VCC V Total Harmonic Distortion (Figure 14) Limit* VEE V 25°C ‘52 ‘53 80 80 80 95 95 95 120 120 120 2.25 4.50 6.00 −2.25 −4.50 −6.00 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600W, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0MHz, RL = 50W, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −40 −40 −40 Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600W, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 25 105 135 RL = 10kW, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600W, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0MHz, RL = 50W, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −60 −60 −60 fin = 1kHz, RL = 10kW, CL = 50pF THD = THDmeasured − THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave Unit ‘51 MHz dB mVPP dB % 2.25 4.50 6.00 −2.25 −4.50 −6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. 180 160 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 300 200 125°C 150 25°C -55°C 100 50 140 120 125°C 100 80 25°C 60 -55°C 40 20 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V Figure 1b. Typical On Resistance, VCC − VEE = 3.0 V www.onsemi.com 6 120 105 100 90 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74HC4051A, MC74HC4052A, MC74HC4053A 125°C 60 25°C 40 -55°C 20 0 75 125°C 60 25°C 45 -55°C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0 0.5 Figure 1c. Typical On Resistance, VCC − VEE = 4.5 V 3.0 3.5 4.0 4.5 5.0 5.5 6.0 60 70 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 2.0 2.5 Figure 1d. Typical On Resistance, VCC − VEE = 6.0 V 80 60 50 125°C 40 30 25°C 20 -55°C 10 0 1.0 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0 1 2 3 4 5 6 7 8 50 125°C 40 25°C 30 -55°C 20 10 0 0 9 1 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2 3 4 5 8 9 10 11 12 Figure 1f. Typical On Resistance, VCC − VEE = 12.0 V PLOTTER - 7 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC − VEE = 9.0 V PROGRAMMABLE POWER SUPPLY 6 MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT VEE GND Figure 2. On Resistance Test Set−Up www.onsemi.com 7 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC VCC 16 VEE ANALOG I/O OFF A VCC VIH OFF VCC COMMON O/I OFF NC OFF VIH 6 7 8 VEE COMMON O/I 6 7 8 VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set−Up VCC VCC VCC 16 A VEE fin dB METER ON N/C COMMON O/I OFF VOS 16 0.1mF ON VCC VCC 16 VEE RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up VCC VIS fin VCC dB METER OFF RL Figure 6. Maximum On Channel Bandwidth, Test Set−Up VOS 16 0.1mF *Includes all probe and jig capacitance CL* 16 RL ON/OFF COMMON O/I ANALOG I/O RL OFF/ON RL RL 6 7 8 VEE VIL or VIH VCC GND CHANNEL SELECT Vin ≤ 1 MHz tr = tf = 6 ns 6 7 8 VEE TEST POINT CL* VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set−Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set−Up www.onsemi.com 8 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC 16 VCC CHANNEL SELECT ON/OFF 50% COMMON O/I ANALOG I/O OFF/ON GND tPLH TEST POINT CL* tPHL ANALOG OUT 6 7 8 50% CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set−Up Channel Select to Analog Out VCC 16 VCC ANALOG IN COMMON O/I ANALOG I/O ON 50% TEST POINT CL* GND tPHL tPLH ANALOG OUT 6 7 8 50% *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out tf tr 90% 50% 10% ENABLE tPZL ANALOG OUT tPLZ 1 VCC GND VCC VCC HIGH IMPEDANCE 10% POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 2 16 1 TEST POINT ON/OFF CL* VOL tPHZ ENABLE 90% 1kW ANALOG I/O 2 50% tPZH ANALOG OUT Figure 10b. Propagation Delay, Test Set−Up Analog In to Analog Out VOH 50% 6 7 8 HIGH IMPEDANCE Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set−Up Enable to Analog Out www.onsemi.com 9 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VIS A VCC 16 RL fin 16 VOS ON/OFF ON COMMON O/I NC ANALOG I/O 0.1mF OFF/ON OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set−Up Figure 13. Power Dissipation Capacitance, Test Set−Up 0 VIS VCC 0.1mF fin ON CL* -20 TO DISTORTION METER -30 -40 dB RL FUNDAMENTAL FREQUENCY -10 VOS 16 -50 DEVICE -60 6 7 8 VEE SOURCE -70 -80 *Includes all probe and jig capacitance -90 - 100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION outputs to VCC or GND through a low value resistor helps minimize crosstalk and feed−through noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC − GND = 2 to 6 volts VEE − GND = 0 to −6 volts VCC − VEE = 2 to 12 volts and VEE ≤ GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and www.onsemi.com 10 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC +5V 16 +5V ANALOG SIGNAL -5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 -5V VEE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V 16 +5V ANALOG SIGNAL VEE ON/OFF 6 7 8 VEE Dx ON/OFF -5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V VEE VEE 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL R VEE +5V 6 7 8 LSTTL/NMOS CIRCUITRY VEE * 2K ≤ R ≤ 10K a. Using Pull−Up Resistors 11 10 9 LSTTL/NMOS CIRCUITRY HCT BUFFER b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 18. Function Diagram, HC4051A www.onsemi.com 11 X0 X1 X2 X3 X4 X5 X6 X7 X MC74HC4051A, MC74HC4052A, MC74HC4053A A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 Figure 19. Function Diagram, HC4052A A 11 3 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 20. Function Diagram, HC4053A www.onsemi.com 12 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74HC4051A, MC74HC4052A, MC74HC4053A ORDERING INFORMATION Device Package MC74HC4051ADG 48 Units / Rail MC74HC4051ADR2G NLV74HC4051ADR2G* Shipping† 2500 Units / Tape & Reel SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC74HC4051AADR2G 2500 Units / Tape & Reel NLV74HC4051AADR2G* 2500 Units / Tape & Reel MC74HC4051ADWG MC74HC4051ADWR2G 48 Units / Rail SOIC−16 WIDE (Pb−Free) NLVHC4051ADWR2G* 1000 Units / Tape & Reel MC74HC4051ADTG MC74HC4051ADTR2G NLVHC4051ADTR2G* 96 Units / Rail TSSOP−16 (Pb−Free) NLVHC4051AADTR2G* NLVHC4051AMNTWG* (In Development) QFN16 (Pb−Free) MC74HC4052ADWR2G NLV74HC4052ADTRG* SOIC−16 WIDE (Pb−Free) TSSOP−16 (Pb−Free) 3000 Units / Tape & Reel 2500 Units / Tape & Reel 48 Units / Rail SOIC−16 WIDE (Pb−Free) NLV74HC4053ADWR2G* 1000 Units / Tape & Reel 1000 Units / Tape & Reel 1000 Units / Tape & Reel MC74HC4053ADTG MC74HC4053ADTR2G 2500 Units / Tape & Reel 2500 Units / Tape & Reel MC74HC4053ADWG MC74HC4053ADWR2G 2500 Units / Tape & Reel 48 Units / Rail SOIC−16 (Pb−Free) NLV74HC4053ADR2G* NLV74HC4053ADWRG* 48 Units / Rail 1000 Units / Tape & Reel 2500 Units / Tape & Reel QFN16 (Pb−Free) MC74HC4053ADG MC74HC4053ADR2G 2500 Units / Tape & Reel 96 Units / Rail NLVHC4052ADTR2G* NLVHC4052AMNTWG* (In Development) 3000 Units / Tape & Reel 2500 Units / Tape & Reel MC74HC4052ADTG MC74HC4052ADTR2G 2500 Units / Tape & Reel 48 Units / Rail SOIC−16 (Pb−Free) NLV74HC4052ADR2G* MC74HC4052ADWG 2500 Units / Tape & Reel 2500 Units / Tape & Reel MC74HC4052ADG MC74HC4052ADR2G 1000 Units / Tape & Reel 96 Units / Rail TSSOP−16 (Pb−Free) NLVHC4053ADTR2G* 2500 Units / Tape & Reel 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW−01 ISSUE O 1 SCALE 2:1 D PIN ONE REFERENCE A B ÉÉÉ ÉÉÉ ÉÉÉ DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS A DETAIL B (A3) 0.10 C NOTE 4 C SIDE VIEW XXXX ALYWG G SEATING PLANE 0.15 C A B XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) D2 16X L K 8 10 DETAIL A 0.15 C A B E2 16X 2 15 e MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.50 BSC 0.85 1.15 3.50 BSC 1.85 2.15 0.50 BSC 0.20 --0.35 0.45 --0.15 GENERIC MARKING DIAGRAM* A1 0.08 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 ÇÇÇ ÇÇÇ ÉÉÉ ÉÉÉ EXPOSED Cu 0.15 C 2X L L1 0.15 C 2X 16X L DATE 11 DEC 2008 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. b 0.10 C A B 1 0.05 C NOTE 3 SOLDERING FOOTPRINT* e/2 3.80 BOTTOM VIEW 2.10 0.50 PITCH 2.80 1.10 1 16X 0.60 16X 0.30 PACKAGE OUTLINE DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON36347E QFN16, 2.5X3.5, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 WB CASE 751G ISSUE E 1 SCALE 1:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* 16 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42567B SOIC−16 WB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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