NLVHC4066ADTR2G

http://onsemi.com This document, MC74HC4066/D has been canceled and replaced by MC74HC4066A/D LAN was sent 9/28/01 MC54/74HC4066 Quad Analog Switch/ Multiplexer/Demultiplexer MC54/74HC4066 High–Performance Silicon–Gate CMOS The MC54/74HC4066 utilizes silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF–channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power–supply range (from VCC to GND). The HC4066 is identical in pinout to the metal–gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal–gate CMOS analog switches. This device is identical in both function and pinout to the HC4016. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage–level translators, see the HC4316. • • • • • • • Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 or HC4016 • Low Noise • Chip Complexity: 44 FETs or 11 Equivalent Gates XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC 2 YA 13 4 3 YB ANALOG OUTPUTS/INPUTS 5 8 9 14 1 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 D SUFFIX SOIC PACKAGE CASE 751A–03 14 1 DT SUFFIX TSSOP PACKAGE CASE 948G–01 14 1 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD MC74HCXXXXDT Ceramic Plastic SOIC TSSOP PIN ASSIGNMENT LOGIC DIAGRAM 1 J SUFFIX CERAMIC PACKAGE CASE 632–08 YA 2 13 YB 3 12 XB B ON/OFF CONTROL C ON/OFF CONTROL GND 4 11 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD 5 10 YD 6 9 YC 7 8 XC XA 1 14 YC FUNCTION TABLE C ON/OFF CONTROL XD D ON/OFF CONTROL 6 11 12 10 YD ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND On/Off Control Input State of Analog Switch L H Off On MC54/74HC4066 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 14.0 V VCC Positive DC Supply Voltage (Referenced to GND) VIS Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V DC Current Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† TSSOP Package† 750 500 450 mW Tstg Storage Temperature – 65 to + 150
C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP) I This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND
(Vin or Vout)
VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
C 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/
C from 65
to 125
C Ceramic DIP: – 10 mW/
C from 100
to 125
C SOIC Package: – 7 mW/
C from 65
to 125
C TSSOP Package: – 6.1 mW/
C from 65
to 125
C ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 12.0 V Analog Input Voltage (Referenced to GND) GND VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch — 1.2 V – 55 + 125
C 0 0 0 0 1000 500 400 250 VCC Positive DC Supply Voltage (Referenced to GND) VIS TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 2.0 V VCC = 4.5 V VCC = 9.0 V VCC = 12.0 V ns * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25
C
85
C
125
C Unit VIH Minimum High–Level Voltage ON/OFF Control Inputs Ron = Per Spec 2.0 4.5 9.0 12.0 1.5 3.15 6.3 8.4 1.5 3.15 6.3 8.4 1.5 3.15 6.3 8.4 V VIL Maximum Low–Level Voltage ON/OFF Control Inputs Ron = Per Spec 2.0 4.5 9.0 12.0 0.3 0.9 1.8 2.4 0.3 0.9 1.8 2.4 0.3 0.9 1.8 2.4 V Iin Maximum Input Leakage Current ON/OFF Control Inputs Vin = VCC or GND 12.0 ± 0.1 ± 1.0 ± 1.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V 6.0 12.0 2 8 20 80 40 160 µA MC54/74HC4066 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Guaranteed Limit Symbol Ron VCC V – 55 to 25
C
85
C
125
C Unit Vin = VIH VIS = VCC to GND IS
2.0 mA (Figures 1, 2) 2.0† 4.5 9.0 12.0 — 170 85 85 — 215 106 106 — 255 130 130 Ω Vin = VIH VIS = VCC or GND (Endpoints) IS
2.0 mA (Figures 1, 2) 2.0 4.5 9.0 12.0 — 85 63 63 — 106 78 78 — 130 95 95 Parameter Test Conditions Maximum “ON” Resistance ∆Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC – GND) IS
2.0 mA 2.0 4.5 9.0 12.0 — 30 20 20 — 35 25 25 — 40 30 30 Ω Ioff Maximum Off–Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or GND Switch Off (Figure 3) 12.0 0.1 0.5 1.0 µA Ion Maximum On–Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or GND (Figure 4) 12.0 0.1 0.5 1.0 µA †At supply voltage (VCC – GND) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage operation, it is recommended that these devices only be used to control digital signals. ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25
C
85
C
125
C Unit tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) 2.0 4.5 9.0 12.0 50 10 10 10 65 13 13 13 75 15 15 15 ns tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 2.0 4.5 9.0 12.0 150 30 30 30 190 38 30 30 225 45 30 30 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 2.0 4.5 9.0 12.0 125 25 25 25 160 32 32 32 185 37 37 37 ns ON/OFF Control Input — 10 10 10 pF Control Input = GND Analog I/O Feedthrough — — 35 1.0 35 1.0 35 1.0 C Maximum Capacitance Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF MC54/74HC4066 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Symbol BW — — — THD Parameter Test Conditions VCC V Limit* 25
C 54/74HC Unit Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 5) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 Ω, CL = 10 pF 4.5 9.0 12.0 150 160 160 MHz Off–Channel Feedthrough Isolation (Figure 6) fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF 4.5 9.0 12.0 – 50 – 50 – 50 dB fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 9.0 12.0 – 40 – 40 – 40 Vin
1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 Ω, CL = 50 pF 4.5 9.0 12.0 60 130 200 RL = 10 kΩ, CL = 10 pF 4.5 9.0 12.0 30 65 100 fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF 4.5 9.0 12.0 – 70 – 70 – 70 fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 9.0 12.0 – 80 – 80 – 80 Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kΩ, CL = 50 pF THD = THDMeasured – THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave * Guaranteed limits not tested. Determined by design and verified by qualification. mVPP dB % 4.5 9.0 12.0 0.10 0.06 0.04 600 120 500 100 400 300 200 -
55°C 25°C 125°C 100 0 0 R on , ON RESISTANCE (OHMS) R on , ON RESISTANCE (OHMS) MC54/74HC4066 80 25°C 60 -
55°C 40 20 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND 125°C 0 Figure 1a. Typical On Resistance, VCC = 2.0 V R on , ON RESISTANCE (OHMS) R on , ON RESISTANCE (OHMS) 120 125°C 70 60 25°C 50 40 -
55°C 30 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 100 80 125°C 60 25°C 40 -
55°C 20 0 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V PLOTTER R on , ON RESISTANCE (OHMS) 80 70 60 PROGRAMMABLE POWER SUPPLY 125°C 50 25°C 40 30 - MINI COMPUTER + DC ANALYZER VCC DEVICE UNDER TEST -
55°C 20 ANALOG IN 10 0 4.5 Figure 1b. Typical On Resistance, VCC = 4.5 V 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12 COMMON OUT GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set–Up 9.0 MC54/74HC4066 VCC VCC 14 GND A VCC 14 A OFF 7 VCC VCC SELECTED CONTROL INPUT VIL 7 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set–Up CL* 7 VIH VOS 14 ON 0.1µF VCC VIS 14 fin SELECTED CONTROL INPUT Figure 4. Maximum On Channel Leakage Current, Test Set–Up VOS VCC N/C ON GND SELECTED CONTROL INPUT fin dB METER 0.1µF OFF CL* RL dB METER SELECTED CONTROL INPUT VCC 7 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On–Channel Bandwidth Test Set–Up VCC VCC/2 Figure 6. Off–Channel Feedthrough Isolation, Test Set–Up VCC/2 14 RL RL OFF/ON VOS IS VCC CL* VCC GND Vin ≤ 1 MHz tr = tf = 6 ns 7 SELECTED CONTROL INPUT ANALOG IN 50% GND tPHL tPLH CONTROL ANALOG OUT 50% *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set–Up Figure 8. Propagation Delays, Analog In to Analog Out MC54/74HC4066 VCC tr 14 ANALOG IN ANALOG OUT ON CL* 7 SELECTED CONTROL INPUT TEST POINT tf VCC 90% 50% 10% CONTROL GND tPZL tPLZ HIGH IMPEDANCE 50% VCC ANALOG OUT tPZH 10% VOL 90% VOH tPHZ 50% HIGH IMPEDANCE *Includes all probe and jig capacitance. Figure 9. Propagation Delay Test Set–Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS 1 POSITIONWHEN TESTING tPHZ AND tPZH VCC 2 POSITIONWHEN TESTING tPLZ AND tPZL 1 2 VCC VCC TEST POINT ON/OFF CL* VOS ON 0.1 µF 1 kΩ 1 2 RL fin 14 14 OFF VCC OR GND RL RL SELECTED CONTROL INPUT SELECTED CONTROL INPUT CL* VCC/2 RL CL* VCC/2 7 7 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set–Up Figure 12. Crosstalk Between Any Two Switches, Test Set–Up VCC A VIS 14 N/C OFF/ON N/C VCC VOS 0.1 µF fin ON RL 7 SELECTED CONTROL INPUT ON/OFF CONTROL CL* TO DISTORTION METER VCC/2 7 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set–Up Figure 14. Total Harmonic Distortion, Test Set–Up MC54/74HC4066 0 -
10 FUNDAMENTAL FREQUENCY -
20 dBm -
30 -
40 -
50 DEVICE -
60 SOURCE -
70 -
80 -
90 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked–up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak–to–peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn–on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MO
sorbs (high current surge protectors). MO
sorbs are fast turn–on devices ideally suited for precise DC protection with no inherent wear out mechanism. VCC VCC = 12 V + 12 V 14 ANALOG I/O ON 0V SELECTED CONTROL INPUT 7 ANALOG O/I Dx + 12 V Figure 16. 12 V Application 16 Dx ON 0V OTHER CONTROL INPUTS (VCC OR GND) VCC Dx VCC Dx SELECTED CONTROL INPUT 7 OTHER CONTROL INPUTS (VCC OR GND) Figure 17. Transient Suppressor Application MC54/74HC4066 +
5 V +
5 V 14 ANALOG SIGNALS R* LSTTL/ NMOS R* R* R* HC4016 14 HCT BUFFER LSTTL/ NMOS 5 6 5 14 CONTROL INPUTS 15 7 ANALOG SIGNALS HC4016 6 CONTROL INPUTS 15 14 ANALOG SIGNALS ANALOG SIGNALS 7 R* = 2 TO 10 kΩ a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VDD = 5 V 13 1 VCC = 5 TO 12 V 16 14 ANALOG SIGNALS 3 HC4016 5 7 ANALOG SIGNALS 2 5 9 4 6 11 6 14 CONTROL INPUTS 10 15 7 MC14504 14 8 Figure 19. TTL/NMOS–to–CMOS Level Converter Analog Signal Peak–to–Peak Greater than 5 V (Also see HC4316) CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 µF 1 2 3 4 CONTROL INPUTS Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier MC54/74HC4066 OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632–08 ISSUE Y -A14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C -T- L DIM A B C D F G J K L M N K SEATING PLANE F G M N D 14 PL 0.25 (0.010) T A M J 14 PL 0.25 (0.010) S M T B S INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0° 15° 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0° 15° 0.51 1.01 N SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE L 14 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F L C J N H G D SEATING PLANE K M DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0
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0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0
10
0.39 1.01 MC54/74HC4066 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 P 7 PL –B– 1 0.25 (0.010) 7 G D 0.25 (0.010) T M F J M K 14 PL M R X 45° C SEATING PLANE B M B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7°  0.228 0.244 0.010 0.019 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G–01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A –V– ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0
8
INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0
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MC54/74HC4066 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800–282–9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. MC74HC4066/D