DATA SHEET
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I/O Expander for I2C Bus
with Interrupt, Low-Power,
16-bit
MARKING
DIAGRAMS
SOIC−24
DW SUFFIX
CASE 751E
PCA9535E, PCA9535EC
The PCA9535E and PCA9535EC devices provide 16 bits of
General Purpose parallel Input / Output (GPIO) expansion through the
I2C−bus / SMBus.
The PCA9535E and PCA9535EC consist of two 8−bit
Configuration (Input or Output selection); Input, Output and Polarity
Inversion (active−HIGH or active−LOW operation) registers. At
power on, all I/Os default to inputs. Each I/O may be configured as
either input or output by writing to its corresponding I/O configuration
bit. The data for each Input or Output is kept in its corresponding Input
or Output register. The Polarity Inversion register may be used to
invert the polarity if the read register. All registers can be read by the
system master.
The PCA9535E, identical to the PCA9655E but with the internal
I/O pull−up resistors removed, has greatly reduced power
consumption when the I/Os are held LOW.
The PCA9535EC is identical to the PCA9535E but with
high−impedance open−drain outputs at all the I/O pins.
The PCA9535E and PCA9535EC provide an open−drain interrupt
output which is activated when any input state differs from its
corresponding input port register state. The interrupt output is used to
indicate to the system master that an input state has changed. The
power−on reset sets the registers to their default values and initializes
the device state machine.
Three hardware pins (AD0, AD1, AD2) are used to configure the
I2C−bus slave address of the device. The I2C−bus slave addresses of
the PCA9535E and PCA9535EC are the same as the PCA9655E. This
allows up to 64 of these devices in any combination to share the same
I2C−bus/SMBus.
Features
September, 2022 − Rev. 9
PCA95
35E(C)G
ALYW
TSSOP−24
DT SUFFIX
CASE 948H
PCA
9535E(C)
ALYWG
G
1
WQFN24
MT SUFFIX
CASE 485BG
XXXX = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
16 I/O Pins which Default to 16 Inputs
I2C SCL Clock Frequencies Supported:
VDD Operating Range: 1.65 V to 5.5 V
SDA Sink Capability: 30 mA
5.5 V Tolerant I/Os
Polarity Inversion Register
Active LOW Interrupt Output
Low Standby Current
Noise Filter on SCL/SDA Inputs
No Glitch on Power−up
Internal Power−on Reset
64 Programmable Slave Addresses using Three
Address Pins
Semiconductor Components Industries, LLC, 2015
PCA9535E(C)
AWLYYWWG
1
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
ESD Performance: 3000 V Human Body Model, 400 V
Machine Model
NLV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
These are Pb−Free Devices
Publication Order Number:
PCA9535E/D
PCA9535E, PCA9535EC
BLOCK DIAGRAM
PCA9535E
PCA9535EC
IO1_0
IO1_1
8−bit
AD0
IO1_2
INPUT/
OUTPUT
PORTS
AD1
AD2
write pulse
IO1_3
IO1_4
IO1_5
IO1_6
read pulse
IO1_7
I2C−BUS/SMBus
CONTROL
SCL
IO0_0
INPUT
FILTER
SDA
IO0_1
8−bit
IO0_2
INPUT/
OUTPUT
PORTS
write pulse
VDD
IO0_3
IO0_4
IO0_5
IO0_6
read pulse
POWER−ON
RESET
IO0_7
VSS
VDD
LP filter
INT
Remark: All I/Os are set as inputs at reset.
Figure 1. Block Diagram
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
output port
register data
configuration
register
D
(1)
VDD
Q1
Q
FF
CK
Q
D
Q
FF
I/O pin
Q2
CK
output port
register
input port
register
D
Q
FF
read pulse
CK
VSS
input port
register data
to INT
polarity inversion
register
data from
shift register
D
Q
FF
write polarity
pulse
polarity
inversion
register data
CK
At power−on reset, all registers return to default values.
1. PCA9535EC I/Os are open−drain only. The portion of the PCA9535E schematic marked inside the dotted line box is not in
PCA9535EC.
Figure 2. Simplified Schematic of I/Os
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2
PCA9535E, PCA9535EC
INT 1
24 VDD
IO0_0 1
AD1 2
23 SDA
AD2 3
22 SCL
IO0_1 2
IO0_0 4
21 AD0
IO0_1 5
20 IO1_7
15 IO1_2
IO0_7 11
14 IO1_1
VSS 12
13 IO1_0
20 SDA
21 VDD
19 SCL
IO1_2 12
16 IO1_3
IO0_6 10
13 IO1_3
IO1_1 11
IO0_5 9
14 IO1_4
IO0_5 6
IO1_0 10
17 IO1_4
15 IO1_5
IO0_4 5
VSS 9
18 IO1_5
16 IO1_6
PCA9535E
PCA9535EC
IO0_3 4
19 IO1_6
IO0_4 8
17 IO1_7
IO0_2 3
IO0_7 8
IO0_3 7
PCA9535E
PCA9535EC
18 AD0
IO0_6 7
IO0_2 6
22 INT
terminal 1
index area
23 AD1
24 AD2
PIN ASSIGNMENT
Transparent top view
(The exposed thermal pad at the bottom
is not connected to internal circuitry)
Figure 3. SOIC24 / TSSOP24
Figure 4. WQFN24
Table 1. PIN DESCRIPTIONS
Pin
Symbol
SOIC24, TSSOP24
WQFN24
Description
INT
1
22
Interrupt Output (active−LOW), connect to GND
recommended if not in use
AD1
2
23
Address Input 1
AD2
3
24
Address Input 2
IO0_0
4
1
Port 0 I/O 0
IO0_1
5
2
Port 0 I/O 1
IO0_2
6
3
Port 0 I/O 2
IO0_3
7
4
Port 0 I/O 3
IO0_4
8
5
Port 0 I/O 4
IO0_5
9
6
Port 0 I/O 5
IO0_6
10
7
Port 0 I/O 6
IO0_7
11
8
Port 0 I/O 7
VSS
12
9
Supply Ground
IO1_0
13
10
Port 1 I/O 0
IO1_1
14
11
Port 1 I/O 1
IO1_2
15
12
Port 1 I/O 2
IO1_3
16
13
Port 1 I/O 3
IO1_4
17
14
Port 1 I/O 4
IO1_5
18
15
Port 1 I/O 5
IO1_6
19
16
Port 1 I/O 6
IO1_7
20
17
Port 1 I/O 7
AD0
21
18
Address Input 0
SCL
22
19
Serial Clock Line
SDA
23
20
Serial Data Line
VDD
24
21
Supply Voltage
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3
PCA9535E, PCA9535EC
Table 2. MAXIMUM RATINGS
Symbol
Value
Unit
VDD
DC Supply Voltage
Parameter
−0.5 to +7.0
V
VI/O
Input / Output Pin Voltage
−0.5 to +7.0
V
II
Input Current
$20
mA
IO
Output Current
$50
mA
IDD
DC Supply Current
$100
mA
IGND
DC Ground Current
$600
mA
PTOT
Total Power Dissipation
600
mW
POUT
Power Dissipation per Output
200
mW
TSTG
Storage Temperature Range
−65 to +150
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
C
TJ
Junction Temperature Under Bias
150
C
qJA
Thermal Resistance (Note 1)
85
91
68
C/W
MSL
Moisture Sensitivity
FR
VESD
ILATCHUP
SOIC−24
TSSOP−24
WQFN24
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @
0.125 in
ESD Withstand Voltage Human Body Mode (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 3000
> 400
N/A
V
Latchup Performance Above VDD and Below GND at 125C (Note 5)
$100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VDD
Positive DC Supply Voltage
VI/O
Switch Input / Output Voltage
TA
Operating Free−Air Temperature
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4
Min
Max
Unit
1.65
5.5
V
0
5.5
V
−55
+125
C
PCA9535E, PCA9535EC
Table 4. DC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V, unless otherwise specified.
TA = −555C to +1255C
Parameter
Symbol
Conditions
Min
Typ
Max
39
39
100
100
1.5
1.65
Unit
SUPPLIES
ISTB
Standby Current (Note 6)
VPOR
Power−On Reset Voltage (Note 7)
Standby mode; no load;
VI = 0 V; fSCL = 0 Hz; I/O = inputs
VI = VDD; fSCL = 0 Hz; I/O = inputs
mA
V
INPUT SCL; INPUT / OUTPUT SDA
VIH
High−Level Input Voltage
0.7 x VDD
VIL
Low−Level Input Voltage
IOL
Low−Level Output Current
VOL = 0.4 V; VDD < 2.3 V
VOL = 0.4 V; VDD w 2.3 V
IL
Leakage Current
VI = VDD or 0 V
CI
Input Capacitance
VI = 0 V
V
0.3 x VDD
10
20
V
mA
4.6
$1
mA
6
pF
I/Os
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IOL
Low−Level Output Current
(Note 8)
IOL(tot)
VOH
IL
CI/O
0.7 x VDD
0.3 x VDD
VOL = 0.5 V; VDD = 1.65 V
8
20
VOL = 0.5 V; VDD = 2.3 V
12
28
VOL = 0.5 V; VDD = 3.0 V
17
35
VOL = 0.5 V; VDD = 4.5 V
25
42
Total Low−Level Output Current
(Note 8)
VOL = 0.5 V; VDD = 4.5 V
High−Level Output Voltage
(PCA9535E Only)
IOH = −3 mA; VDD = 1.65 V
1.2
IOH = −4 mA; VDD = 1.65 V
1.1
IOH = −8 mA; VDD = 2.3 V
1.8
IOH = −10 mA; VDD = 2.3 V
1.7
IOH = −8 mA; VDD = 3.0 V
2.6
IOH = −10 mA; VDD = 3.0 V
2.5
IOH = −8 mA; VDD = 4.5 V
4.1
IOH = −10 mA; VDD = 4.5 V
4.0
Input Leakage Current
V
400
mA
V
VDD = 5.5 V; VI = VDD or 0 V
Input / Output Capacitance
(Note 9)
V
mA
3.7
$1
mA
5
pF
INTERRUPT (INT)
IOL
Low−Level Output Current
CO
Output Capacitance
VOL = 0.4 V
6
mA
2.1
5
pF
INPUTS AD0, AD1, AD2
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IL
Leakage Current
CI
Input Capacitance
0.7 x VDD
V
VI = VDD or 0 V
2.4
0.3 x VDD
V
$1
mA
5
pF
6. The device is in standby mode after an I2C stop command.
7. The power−on reset circuit resets the I2C bus logic with VDD < VPOR and set all I/Os to logic 1 upon power−up. Thereafter, VDD must
be lower than 0.2 V to reset the part.
8. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
9. The value is not tested, but verified on sampling basis.
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PCA9535E, PCA9535EC
Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V; TA = −55C to +125C, unless otherwise specified.
Standard Mode
Parameter
Symbol
Fast Mode
Fast Mode +
Min
Max
Min
Max
Min
Max
Unit
0
0.1
0
0.4
0
1.0
MHz
fSCL
SCL Clock Frequency
tBUF
Bus−Free Time between a STOP and START
Condition
4.7
1.3
0.5
ms
tHD:STA
Hold Time (Repeated) START Condition
4.0
0.6
0.26
ms
tSU:STA
Setup Time for a Repeated START Condition
4.7
0.6
0.26
ms
tSU:STO
Setup Time for STOP Condition
4.0
0.6
0.26
ms
tHD:DAT
Data Hold Time
tVD:ACK
Data Valid Acknowledge Time (Note 10)
0.3
0
tVD:DAT
Data Valid Time (Note 11)
300
tSU:DAT
Data Setup Time
tLOW
tHIGH
0
3.45
0.1
0
0.9
ns
0.05
0.45
ms
50
50
450
ns
250
100
50
ns
LOW Period of SCL
4.7
1.3
0.5
ms
HIGH Period of SCL
4.0
0.6
0.26
ms
tf
Fall Time of SDA and SCL (Notes 13 and 14)
300
20 +
0.1Cb
(Note 12)
300
120
ns
tr
Rise Time of SDA and SCL
1000
20 +
0.1Cb
(Note 12)
300
120
ns
50
50
50
ns
200
350
550
200
350
550
200
350
550
ns
tSP
Pulse Width of Spikes Suppressed by Input
Filter (Note 15)
PORT TIMING: CL v 100 pF (See Figures 6, 9 and 10)
tV(Q)
Data Output Valid Time (VDD = 4.5 V to 5.5 V)
(VDD = 2.3 V to 4.5 V)
(VDD = 1.65 V to 2.3 V)
tSU(D)
Data Input Setup Time
100
100
100
ns
tH(D)
Data Input Hold Time
1
1
1
ms
INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10)
tV(INT_N)
tRST(INT_N)
Data Valid Time
4
4
4
ms
Reset Delay Time
4
4
4
ms
10. tVD:ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
11. tVD:DAT = minimum time for SDA data out to be valid following SCL LOW.
12. Cb = total capacitance of one bus line in pF.
13. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge
the undefined region SCL’s falling edge.
14. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
15. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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PCA9535E, PCA9535EC
Device Address
slave address
Before the bus master can access a slave device, it must
send the address of the slave it is accessing and the operation
it wants to perform (read or write) following a START
condition. The slave address of the PCA9535E and
PCA9535EC is shown in Figure 5. Address pins AD2, AD1,
and AD0 choose 1 of 64 slave addresses. To conserve power,
no internal pull−up resistors are provided on AD2, AD1, and
AD0.
A logic 1 on the last bit of the first byte selects a read
operation while a logic 0 selects a write operation.
A6
A5
A4
A3
A2
A1
A0
R/W
programmable
Figure 5. PCA9535E and PCA9535EC Device Address
Table 6. PCA9535E AND PCA9535EC ADDRESS MAP
Address Input
Slave Address
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
HEX
GND
SCL
GND
0
0
1
0
0
0
0
20h
GND
SCL
VDD
0
0
1
0
0
0
1
22h
GND
SDA
GND
0
0
1
0
0
1
0
24h
GND
SDA
VDD
0
0
1
0
0
1
1
26h
VDD
SCL
GND
0
0
1
0
1
0
0
28h
VDD
SCL
VDD
0
0
1
0
1
0
1
2Ah
VDD
SDA
GND
0
0
1
0
1
1
0
2Ch
VDD
SDA
VDD
0
0
1
0
1
1
1
2Eh
GND
SCL
SCL
0
0
1
1
0
0
0
30h
GND
SCL
SDA
0
0
1
1
0
0
1
32h
GND
SDA
SCL
0
0
1
1
0
1
0
34h
GND
SDA
SDA
0
0
1
1
0
1
1
36h
VDD
SCL
SCL
0
0
1
1
1
0
0
38h
VDD
SCL
SDA
0
0
1
1
1
0
1
3Ah
VDD
SDA
SCL
0
0
1
1
1
1
0
3Ch
VDD
SDA
SDA
0
0
1
1
1
1
1
3Eh
GND
GND
GND
0
1
0
0
0
0
0
40h
GND
GND
VDD
0
1
0
0
0
0
1
42h
GND
VDD
GND
0
1
0
0
0
1
0
44h
GND
VDD
VDD
0
1
0
0
0
1
1
46h
VDD
GND
GND
0
1
0
0
1
0
0
48h
VDD
GND
VDD
0
1
0
0
1
0
1
4Ah
VDD
VDD
GND
0
1
0
0
1
1
0
4Ch
VDD
VDD
VDD
0
1
0
0
1
1
1
4Eh
GND
GND
SCL
0
1
0
1
0
0
0
50h
GND
GND
SDA
0
1
0
1
0
0
1
52h
GND
VDD
SCL
0
1
0
1
0
1
0
54h
GND
VDD
SDA
0
1
0
1
0
1
1
56h
VDD
GND
SCL
0
1
0
1
1
0
0
58h
VDD
GND
SDA
0
1
0
1
1
0
1
5Ah
VDD
VDD
SCL
0
1
0
1
1
1
0
5Ch
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PCA9535E, PCA9535EC
Table 6. PCA9535E AND PCA9535EC ADDRESS MAP
Address Input
Slave Address
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
HEX
VDD
VDD
SDA
0
1
0
1
1
1
1
5Eh
SCL
SCL
GND
1
0
1
0
0
0
0
A0h
SCL
SCL
VDD
1
0
1
0
0
0
1
A2h
SCL
SDA
GND
1
0
1
0
0
1
0
A4h
SCL
SDA
VDD
1
0
1
0
0
1
1
A6h
SDA
SCL
GND
1
0
1
0
1
0
0
A8h
SDA
SCL
VDD
1
0
1
0
1
0
1
AAh
SDA
SDA
GND
1
0
1
0
1
1
0
ACh
SDA
SDA
VDD
1
0
1
0
1
1
1
AEh
SCL
SCL
SCL
1
0
1
1
0
0
0
B0h
SCL
SCL
SDA
1
0
1
1
0
0
1
B2h
SCL
SDA
SCL
1
0
1
1
0
1
0
B4h
SCL
SDA
SDA
1
0
1
1
0
1
1
B6h
SDA
SCL
SCL
1
0
1
1
1
0
0
B8h
SDA
SCL
SDA
1
0
1
1
1
0
1
BAh
SDA
SDA
SCL
1
0
1
1
1
1
0
BCh
SDA
SDA
SDA
1
0
1
1
1
1
1
BEh
SCL
GND
GND
1
1
0
0
0
0
0
C0h
SCL
GND
VDD
1
1
0
0
0
0
1
C2h
SCL
VDD
GND
1
1
0
0
0
1
0
C4h
SCL
VDD
VDD
1
1
0
0
0
1
1
C6h
SDA
GND
GND
1
1
0
0
1
0
0
C8h
SDA
GND
VDD
1
1
0
0
1
0
1
CAh
SDA
VDD
GND
1
1
0
0
1
1
0
CCh
SDA
VDD
VDD
1
1
0
0
1
1
1
CEh
SCL
GND
SCL
1
1
1
0
0
0
0
E0h
SCL
GND
SDA
1
1
1
0
0
0
1
E2h
SCL
VDD
SCL
1
1
1
0
0
1
0
E4h
SCL
VDD
SDA
1
1
1
0
0
1
1
E6h
SDA
GND
SCL
1
1
1
0
1
0
0
E8h
SDA
GND
SDA
1
1
1
0
1
0
1
EAh
SDA
VDD
SCL
1
1
1
0
1
1
0
ECh
SDA
VDD
SDA
1
1
1
0
1
1
1
EEh
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PCA9535E, PCA9535EC
REGISTERS
Command Byte
During a write transmission, the address byte is followed
by the command byte. The command byte determines which
of the following registers will be written or read.
Table 7. COMMAND BYTE
COMMAND
REGISTER
0
Input Port 0
1
Input Port 1
2
Output Port 0
3
Output Port 1
4
Polarity Inversion Port 0
5
Polarity Inversion Port 1
6
Configuration Port 0
7
Configuration Port 1
Registers 0 and 1: Input Port Registers
The externally−applied logic level determines the default
value ‘X’.
These registers are input−only. They reflect the incoming
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Registers 6 or 7. Writes
to these registers have no effect.
Table 8. INPUT PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 9. INPUT PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
Registers 2 and 3: Output Port Registers
as inputs. In turn, reads from these registers reflect the values
that are in the flip−flops controlling the output selection, not
the actual pin values.
These registers are output−only. They reflect the outgoing
logic levels of the pins defined as outputs by Registers 6 and
7. Bit values in these registers have no effect on pins defined
Table 10. OUTPUT PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 11. OUTPUT PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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9
PCA9535E, PCA9535EC
Registers 4 and 5: Polarity Inversion Registers
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
These registers allow the polarity of the data in the input
port registers to be inverted. The input port data polarity will
Table 12. POLARITY INVERSION PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 13. POLARITY INVERSION PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
Registers 6 and 7: Configuration Registers
pin is enabled as an input with the output driver in
high−impedance. When a bit is cleared (written with ‘0’),
the corresponding port pin is enabled as an output. At reset,
the device’s ports are inputs.
The I/O pin directions are configured through the
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
Table 14. CONFIGURATION PORT 0 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 15. CONFIGURATION PORT 1 REGISTER
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
Power−on Reset
high−impedance input. The input voltage may be raised
above VDD to a maximum of 5.5 V. In the case of
PCA9535EC, FET Q1 has been removed and the
open−drain FET Q2 will function the same as PCA9535E.
When the I/O pin is configured as an output on the
PCA9535E, then either Q1 or Q2 is enabled, depending on
the state of the output port register. With the PCA9535EC,
an external pullup is required to pull the I/O pin HIGH when
its corresponding output port register bit is a 1. Care should
be exercised if an external voltage is applied to an I/O
configured as an output because of the low−impedance path
that exists between the pin and either VDD or VSS.
Upon application of power, an internal Power−On Reset
(POR) holds the PCA9535E/PCA9535EC in a reset
condition while VDD is ramping up. When VDD has reached
VPOR, the reset condition is released and the
PCA9535E/PCA9535EC registers and SMBus state
machine will initialize to their default states. The reset is
typically completed by the POR and the part enabled by the
time the power supply is above VPOR. However, when doing
a power reset cycle, it is necessary to lower the power supply
below 0.2 V, and then restored to the operating voltage.
Please refer to application note AND9169/D for
recommended power−up and power−cycle reset profiles.
I/O Port (See Figure 2)
When an I/O pin is configured as an input on the
PCA9535E, FETs Q1 and Q2 are off, creating a
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10
PCA9535E, PCA9535EC
BUS TRANSACTIONS
Writing to the Port Registers
operate as four register pairs: Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. Data
bytes are sent alternately to each register in a register pair
(see Figures 6 and 7). For example, if one byte is sent to
Output Port 1 (register 3), then the next byte will be stored
in Output Port 0 (register 2). There is no limitation on the
number of data bytes sent in one write transmission. In this
way, each 8−bit register may be updated independently of
the other registers.
To transmit data to the PCA9535E/PCA9535EC, the bus
master must first send the device address with the least
significant bit set to logic 0 (see Figure 5 “PCA9535E and
PCA9535EC device address”). The command byte is sent
after the address and determines which registers will receive
the data following the command byte.
There
are
eight
registers
within
the
PCA9535E/PCA9535EC. These registers are configured to
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
0
0
0
0
0
0
data to port 1
data to port 0
1
0 A 0.7
0.0 A 1.7
DATA 0
1.0 A
acknowledge
from slave
acknowledge
from slave
R/W acknowledge
from slave
DATA 1
P
STOP
condition
write to port
tv(Q)
data out
from port 0
tv(Q)
data out
from port 1
DATA VALID
Figure 6. Write to Output Port Registers
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
data to register
command byte
A
0
0
0
0
0
1
MSB
1
0
R/W acknowledge
from slave
A
data to register
MSB
LSB
DATA 0
acknowledge
from slave
A
acknowledge
from slave
LSB
DATA 1
A
P
STOP
condition
Figure 7. Write to Configuration Registers
Reading the Port Registers
by the PCA9535E/PCA9535EC (see Figures 8, 9 and 10).
Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read,
additional bytes may be read but with data alternately
coming from each register in the pair. For example, if you
read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data
bytes received in one read transmission but the bus master
must not acknowledge the data for the final byte received.
To read data from the PCA9535E/PCA9535EC, the bus
master must first send the PCA9535E/PCA9535EC address
with the least significant bit set to logic 0 (see Figure 5
“PCA9535E and PCA9535EC device address”). The
command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
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11
PCA9535E, PCA9535EC
slave address
SDA
S
A6 A5 A4 A3 A2 A1 A0
START condition
0
A
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
slave address
(cont.)
MSB
A6 A5 A4 A3 A2 A1 A0
S
(repeated)
START condition
(cont.)
A
COMMAND BYTE
1
A
data from upper or
lower byte of register
A
LSB
DATA (last byte)
acknowledge
from master
R/W
acknowledge
from slave
MSB
LSB
DATA (first byte)
NA P
no acknowledge
from master
STOP
condition
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
Remark: Transfer can be stopped at any time by a STOP condition.
Figure 8. Read from Register
SCL
1 2 3 4 5 6 7 8 9
slave address
I0.x
I1.x
I0.x
I1.x
STOP condition
SDA S A6 A5 A4 A3 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
START condition
read from port 0
R/W
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t v(INT_N)
t rst(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 9. Read from Input Port Register, Scenario 1
SCL
1 2 3 4 5 6 7 8 9
slave address
R/W
I0.x
SDA S A6 A5A4 A3 A2 A1 A0 1 A
START condition
acknowledge
from slave
DATA 00
I1.x
A
DATA 10
A
acknowledge
from master
tsu(D)
acknowledge
from master
th(D)
I0.x
DATA 03
I1.x
A
acknowledge
from master
DATA 12
STOP condition
1 P
non acknowledge
from master
read from port 0
data into port 0
DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
read from port 1
data into port 1
DATA 10
DATA 11
DATA 12
INT
t v(INT_N)
t rst(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 10. Read from Input Port Register, Scenario 2
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12
PCA9535E, PCA9535EC
Interrupt Output
each 8−bit port is read independently, the interrupt caused by
Port 0 will not be cleared by a read of Port 1 or the other way
around.
Remark: Changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
The open−drain interrupt output is activated when an I/O
pin configured as an input changes state. The interrupt is
deactivated when the input pin returns to its previous state
or when the Input Port register is read (see Figure 9). A pin
configured as an output cannot cause an interrupt. Since
APPLICATION INFORMATION
V DD
(5 V)
10 kW
10 kW
10 kW
2 kW
V DD
SUB−SYSTEM 1
(e.g., temp sensor)
100 kW
(x3)
V DD
MASTER
CONTROLLER
SCL
SCL
SDA
SDA
INT
INT
PCA9535E
IO0_0
SUB−SYSTEM 2
(e.g., counter)
IO0_1
RESET
IO0_2
INT
IO0_3
GND
A
IO0_4
controlled
switch
(e.g., 7SB or FST)
ENABLE
IO0_5
B
IO0_6
IO0_7
SUB−SYSTEM 3
(e.g., alarm system)
IO1_0
IO1_1
10 DIGIT
NUMERIC
KEYPAD
IO1_2
IO1_3
IO1_4
AD2
V DD
IO1_5
AD1
ALARM
IO1_6
IO1_7
AD0
V SS
Device address configured as 0100 000xb for this example.
IO0_0, IO0_2, IO0_3 configured as outputs.
IO0_1, IO0_4, IO0_5 configured as inputs.
IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
Figure 11. Typical Application
Minimizing IDD When the I/Os are Used to Control
LEDs
pin voltages be greater than or equal to VDD when the LED
is off. This would minimize current consumption. Figure 12
shows a high value resistor in parallel with the LED.
Figure 13 shows VDD less than the LED supply voltage by
at least 1.2 V. Both of these methods maintain the I/O VI at
or above VDD and prevents additional supply current
consumption when the LED is off.
This concern does not occur for the PCA9535EC because
the PCA9535EC I/O pins are open−drain.
To use the PCA9535E I/Os to control LEDs, the I/Os are
normally connected to VDD through a resistor as shown in
Figure 11. The LED acts as a diode. When the LED is off,
the I/O VI is about 1.2 V less than VDD. The supply current,
IDD, increases as VI becomes lower than VDD.
For applications requiring low current consumption, such
as battery power applications, it is recommended that the I/O
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13
PCA9535E, PCA9535EC
VDD
LED
5V
3.3 V
VDD
VDD
100 kW
LEDn
LED
LEDn
Figure 12. High Value Resistor in Parallel
with the LED
Figure 13. Device Supplied by a Lower Voltage
Characteristics of the I2C−bus
Bit transfer
The I2C−bus is meant for 2−way, 2−line communication
between different ICs or modules. The two lines are the
serial data line (SDA) and the serial clock line (SCL). Both
lines must be connected to a positive supply via a pull−up
resistor when connected to the output stages of a device.
Data transfer may only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse. Changes in the data line during the
HIGH period of the clock pulse will be interpreted as control
signals (see Figure 14).
SDA
SCL
change
of data
allowed
data line
stable;
data valid
Figure 14. Bit Transfer
START and STOP conditions
HIGH. A STOP condition (P) occurs when there is a
LOW−to−HIGH transition of the data line while the clock is
HIGH (see Figure 15).
Both data and clock lines remain HIGH when the bus is
not busy. A START condition (S) occurs when there is a
HIGH−to−LOW transition of the data line while the clock is
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
Figure 15. Definition of START and STOP Conditions
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14
PCA9535E, PCA9535EC
System Configuration
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 16).
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C−BUS
MULTIPLEXER
SLAVE
Figure 16. System Configuration
Acknowledge
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; set−up time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8−bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
S
8
9
clock pulse for
acknowledgement
START
condition
Figure 17. Acknowledgement of the I2C Bus
Timing and Test Setup
SDA
tr
tBUF
tf
tHD;STA
tSP
tLOW
SCL
tHD;STA
P
S
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Sr
Figure 18. Definition of Timing on the I2C Bus
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15
tSU;STO
P
PCA9535E, PCA9535EC
protocol
bit 7
MSB
(A7)
START
condition
(S)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
acknowledge
(A)
(P)
1/f
SCL
SCL
tBUF
tf
tr
SDA
tSU;DAT
tHD;STA
tVD;DAT
tHD;DAT
tVD;ACK
tSU;STO
Rise and fall times refer to VIL and VIH
Figure 19. I2C Bus Timing Diagram
SCL
SCL
tv(Q)
tv(Q)
IOn
IOn
Figure 20. tV(Q) Timing
VDD
PULSE
GENERATOR
VI
RL
500 W
VO
VDD
open
GND
DUT
CL
50 pF
RT
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.
Figure 21. Test Circuitry for Switching Times
RL
from output under test
500 W
CL
50 pF
RL
500 W
Figure 22. Load Circuit
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16
S1
2VDD
open
GND
PCA9535E, PCA9535EC
ORDERING INFORMATION
Package
Shipping†
PCA9535EDWR2G
SOIC−24
(Pb−Free)
1000 / Tape & Reel
PCA9535EDTR2G,
NLVPCA9535EDTR2G*
TSSOP−24
(Pb−Free)
2500 / Tape & Reel
PCA9535EMTTXG,
NLVPCA9535EMTTXG*
WQFN24
(Pb−Free)
3000 / Tape & Reel
PCA9535ECDWR2G
SOIC−24
(Pb−Free)
1000 / Tape & Reel
PCA9535ECDTR2G
TSSOP−24
(Pb−Free)
2500 / Tape & Reel
PCA9535ECMTTXG
WQFN24
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−24 WB
CASE 751E−04
ISSUE F
DATE 03 JUL 2012
SCALE 1:1
D
24
E
H
A
B
0.25 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD AND ARE MEASURED BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
13
E1
1
L
12
C
DETAIL A
24X b
PIN 1
INDICATOR
0.25
TOP VIEW
M
C A
S
B
S
h
x 45 _
A
e
A1
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
h
L
M
NOTE 3
C
c
SEATING
PLANE
NOTE 3
M
DETAIL A
END VIEW
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
24X
24X
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
15.25
15.54
10.30 BSC
7.40
7.60
1.27 BSC
0.25
0.75
0.41
0.90
0_
8_
1.62
0.52
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
AWLYYWWG
11.00
1
1
XXXXX
A
WL
YY
WW
G
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42344B
SOIC−24 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN24 4x4, 0.5P
CASE 485BG
ISSUE A
1
DATE 17 APR 2012
SCALE 2:1
B
A
D
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
0.15 C
0.15 C
TOP VIEW
NOTE 4
DETAIL A
D2
7
24X
A1
SIDE VIEW
ÉÉ
ÉÉ
MOLD CMPD
ALTERNATE
CONSTRUCTION
A3
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
DETAIL B
A
0.10 C
0.08 C
L
L
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
C
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
XXXXX
XXXXX
ALYWG
G
K
13
L
E2
1
19
e
e/2
BOTTOM VIEW
24X
b
0.10 C A B
0.05 C
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.00
2.20
4.00 BSC
2.00
2.20
0.50 BSC
0.20
−−−
0.30
0.50
0.00
0.15
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
NOTE 3
MOUNTING FOOTPRINT
4.30
2.26
24X
0.63
1
2.26
4.30
PACKAGE
OUTLINE
0.50
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
98AON48315E
WQFN24 4X4, 0.5P
24X
0.30
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP24 7.8x4.4, 0.65P
CASE 948H
ISSUE B
DATE 21 JUN 2012
SCALE 1:1
NOTE 4
L2
NOTE 6
B
NOTE 5
A
D
NOTE 6
24
13
GAUGE
PLANE
E1
L
E
PIN 1
1
REFERENCE
DETAIL A
12
e
24X
TOP VIEW
0.15 C B
b
0.10
S
2X 12 TIPS
C B
M
S
A
S
NOTE 3
A
0.05 C
A1
0.10 C
24X
C
SIDE VIEW
SEATING
PLANE
H
DETAIL A
c
END VIEW
M
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MILLIMETERS
MAX
MIN
1.20
--0.05
0.15
0.19
0.30
0.09
0.20
7.90
7.70
6.40 BSC
4.30
4.50
0.65 BSC
0.50
0.75
0.25 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT
24X
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL BE 0.08 MAX AT MMC. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15
PER SIDE. DIMENSION D IS DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE. DIMENSION E1 IS DETERMINED
AT DATUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
0.42
XXXXX
XXXXG
ALYW
24X
1.15
6.70
0.65
PITCH
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70248A
TSSOP24 7.8X4.4, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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