2-Input AND Gate with
Open Drain Output
MC74VHC1G09
The MC74VHC1G09 is an advanced high speed CMOS 2−input
AND gate with open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The input structures provide protection when voltages up to 5.5 V
are applied, regardless of the supply voltage. This allows the device to
be used to interface 5 V circuits to 3 V circuits. The output structures
also provide protection when VCC = 0 V and when the output voltage
exceeds VCC. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
Designed for 2.0 V to 5.5 V VCC Operation
4.3 ns tPD at 5 V (typ)
Inputs/Outputs Over−Voltage Tolerant up to 5.5 V
IOFF Supports Partial Power Down Protection
Source/Sink 8 mA at 3.0 V
Available in SC−88A, SC−74A, TSOP−5, SOT−553, SOT−953 and
UDFN6 Packages
Chip Complexity < 100 FETs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A
B
&
XX MG
G
SC−74A
DBV SUFFIX
CASE 318BQ
XXX MG
G
5
TSOP−5
DT SUFFIX
CASE 483
5
1
XX MG
G
1
SOT−553
XV5 SUFFIX
CASE 463B
SOT−953
P5 SUFFIX
CASE 527AE
Y
Figure 1. Logic Symbol
SC−88A
DF SUFFIX
CASE 419A
XX MG
G
XM
1
UDFN6
1.45 x 1.0
CASE 517AQ
1
UDFN6
1.0 x 1.0
CASE 517BX
XX
M
G
XM
XM
1
= Specific Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
October, 2020 − Rev. 20
1
Publication Order Number:
MC74VHC1G09/D
MC74VHC1G09
B
VCC
1
5
OVT
A
VCC
A
5
1
GND
GND
4
3
6
VCC
OVT
A
2
5
NC
GND
3
4
Y
Y
B
Y
1
OVT
2
2
B
4
3
SOT−953
(SC−88A/SOT−553/
TSOP−5/ SC−74A)
UDFN6
Figure 2. Pinout (Top View)
PIN ASSIGNMENT
(SC−88A/SOT−553/ TSOP−5/SC−74A)
PIN ASSIGNMENT (SOT−953)
PIN ASSIGNMENT (UDFN)
Pin
Function
Pin
Function
Pin
Function
1
B
1
A
1
B
2
A
2
GND
2
A
3
GND
3
B
3
GND
4
Y
4
Y
4
Y
5
VCC
5
VCC
5
NC
6
VCC
FUNCTION TABLE
Input
Output
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
Z
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2
MC74VHC1G09
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
−0.5 to +7.0
−0.5 to +6.5
V
VIN
DC Input Voltage
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
−0.5 to +7.0
−0.5 to +6.5
V
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC + 0.5
−0.5 to +7.0
−0.5 to +7.0
V
DC Output Voltage
Active−Mode (High or Low State)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC + 0.5
−0.5 to +6.5
−0.5 to +6.5
V
VIN < GND
−20
mA
VOUT < GND
−20
mA
VOUT
Characteristics
DC Output Voltage
TSOP−5, SC−88A (NLV)
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOUT
DC Output Source/Sink Current
$25
mA
DC Supply Current per Supply Pin or Ground Pin
$50
mA
−65 to +150
°C
ICC or IGND
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 secs
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
SC−88A
SC−74A
SOT−553
SOT−953
UDFN6
377
320
324
254
154
°C/W
PD
Power Dissipation in Still Air
SC−88A
SC−74A
SOT−553
SOT−953
UDFN6
332
390
386
491
812
mW
Level 1
−
MSL
Moisture Sensitivity
FR
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
−
ESD Withstand Voltage (Note 3)
Human Body Model
Charged Device Model
2000
1000
V
$100
mA
VESD
ILatchup
Latchup Performance (Note 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10mm−by−1inch, 2 ounce copper trace no air flow per JESD51−7.
3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.
4. Tested to EIA/JESD78 Class II.
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3
MC74VHC1G09
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC
Positive DC Supply Voltage
VIN
DC Input Voltage
VOUT
TA
tr , tf
Min
Max
Unit
2.0
5.5
V
0
5.5
V
DC Output Voltage
TSOP−5, SC−88A (NLV)
0
VCC
V
DC Output Voltage
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
0
0
0
VCC
5.5
5.5
−55
+125
Operating Temperature Range
Input Rise and Fall Time
TSOP−5, SC−88A (NLV)
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
100
20
Input Rise and Fall Time
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
VCC = 2.0 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
0
0
20
20
10
5
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (MC74VHC1G09)
Symbol
VIH
VIL
VOL
Parameter
Test
Conditions
High−Level Input
Voltage
Low−Level Input
Voltage
TA = 25°C
−40°C ≤ TA ≤ 85°C
−55°C ≤ TA ≤ 125°C
VCC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
2.0
1.5
−
−
1.5
−
1.5
−
V
3.0
2.1
−
−
2.1
−
2.1
−
4.5
3.15
−
−
3.15
−
3.15
−
5.5
3.85
−
−
3.85
−
3.85
−
2.0
−
−
0.5
−
0.5
−
0.5
3.0
−
−
0.9
−
0.9
−
0.9
4.5
−
−
1.35
−
1.35
−
1.35
5.5
−
−
1.65
−
1.65
−
1.65
2.0
3.0
4.5
3.0
4.5
−
−
−
−
−
0.0
0.0
0.0
−
−
0.1
0.1
0.1
0.36
0.36
−
−
−
−
−
0.1
0.1
0.1
0.44
0.44
−
−
−
−
−
0.1
0.1
0.1
0.52
0.52
V
Low−Level Output
Voltage
VIN = VIH or VIL
IOL = 50 mA
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
IOL = 8 mA
IIN
Input Leakage
Current
VIN = 5.5 V or
GND
2.0
to 5.5
−
−
±0.1
−
±1.0
−
$1.0
mA
IOZ
3−State Output
Leakage Current
VOUT = 0 V to
5.5 V
5.5
−
−
±0.25
−
$2.5
−
$2.5
mA
IOFF
Power Off Leakage
Current
VIN = 5.5 V or
VOUT = 5.5 V
0
−
−
1.0
−
10
−
10
mA
ICC
Quiescent Supply
Current
VIN = VCC or
GND
5.5
−
−
1.0
−
20
−
40
mA
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4
V
MC74VHC1G09
AC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
Parameter
Conditions
VCC (V)
Min
Typ
tPZL
Propagation Delay,
(A or B) to Y
(Figures 3 and 4)
CL = 15 pF
3.0 to 3.6
−
−
CL = 50 pF
CL = 15 pF
4.5 to 5.5
CL = 50 pF
tPLZ
Propagation Delay,
(A or B) to Y
(Figures 3 and 4)
CL = 15 pF
3.0 to 3.6
CL = 50 pF
CL = 15 pF
4.5 to 5.5
CL = 50 pF
CIN
Input Capacitance
COUT
Output Capacitance
Output in
High
Impedance
State
CPD
Power Dissipation Capacitance (Note 5)
−40°C ≤ TA ≤ 85°C
−55°C ≤ TA ≤ 125°C
Max
Min
Max
Min
Max
Unit
6.2
8.8
−
10.5
−
12.5
ns
8.7
12.3
−
14.0
−
16.5
−
4.3
5.9
−
7.0
−
9.0
−
5.8
7.9
−
9.0
−
11.0
−
6.5
9.7
−
11.5
−
14.5
−
8.7
12.3
−
14.0
−
16.5
−
4.8
6.8
−
8.0
−
10.0
−
5.8
7.9
−
9.0
−
11.0
−
4.0
10
−
10
−
10
pF
−
6.0
−
−
−
−
−
pF
ns
Typical @ 25°C, VCC = 5.0 V
8.0
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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5
MC74VHC1G09
OPEN
VCC
Test
Switch
Position
CL, pF
RL, W
tPLH / tPHL
Open
See AC Characteristics Table
X
tPLZ / tPZL
VCC
1k
tPHZ / tPZH
GND
1k
GND
RL
OUTPUT
DUT
RT
X = Don’t Care
CL *
CL includes probe and jig capacitance
RT is ZOUT of pulse generator (typically 50 W)
f = 1 MHz
Figure 3. Test Circuit
tr = 3 ns
tf = 3 ns
90%
90%
Vmi
INPUT
Vmi
INPUT
Vmi
10%
10%
tPHL
Vmi
GND
GND
tPZL
tPLH
Vmo
OUTPUT
VCC
VCC
tPLZ
Vmo
OUTPUT
Vmo
VOL + VY
VOL
VOL
tPLH
OUTPUT
tPHL
Vmo
~VCC
VOH
tPZH
VOH
Vmo
tPHZ
VOH
VOH − VY
Vmo
OUTPUT
VOL
~0 V
Figure 4. Switching Waveforms
Vmo, V
VCC, V
Vmi, V
tPLH, tPHL
3.0 to 3.6
VCC/2
VCC/2
VCC/2
0.3
4.5 to 5.5
VCC/2
VCC/2
VCC/2
0.3
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6
tPZL, tPLZ, tPZH, tPHZ
VY, V
MC74VHC1G09
ORDERING INFORMATION
Packages
Specific Device Code
Pin 1 Orientation
(See below)
Shipping†
MC74VHC1G09DFT1G
SC−88A
VX
Q2
3000 / Tape & Reel
MC74VHC1G09DFT2G
SC−88A
VX
Q4
3000 / Tape & Reel
NLVVHC1G09DFT1G*
SC−88A
VX
Q2
3000 / Tape & Reel
NLVVHC1G09DFT2G*
SC−88A
VX
Q4
3000 / Tape & Reel
MC74VHC1G09DBVT1G
SC−74A
VX
Q4
3000 / Tape & Reel
MC74VHC1G09DTT1G
TSOP−5
VX
Q4
3000 / Tape & Reel
NLV74VHC1G09DTT1G*
TSOP−5
VXR
Q4
3000 / Tape & Reel
MC74VHC1G09XV5T2G
(In Development)
SOT−553
TBD
Q4
4000 / Tape & Reel
MC74VHC1G09P5T5G
(In Development)
SOT−953
TBD
Q2
8000 / Tape & Reel
MC74VHC1G09MU1TCG
(In Development)
UDFN6, 1.45 x 1.0, 0.5P
TBD
Q4
3000 / Tape & Reel
MC74VHC1G09MU3TCG
(In Development)
UDFN6, 1.0 x 1.0, 0.35P
TBD
Q4
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
Pin 1 Orientation in Tape and Reel
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7
MC74VHC1G09
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDER FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G09
PACKAGE DIMENSIONS
SC−74A
CASE 318BQ
ISSUE B
5X
b
0.20 C A B
E1
5
M
4
1
2
E
3
B
0.05
A1
L
DETAIL A
e
A
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE.
TOP VIEW
A
SIDE VIEW
C
DETAIL A
c
SEATING
PLANE
END VIEW
DIM
A
A1
b
c
D
E
E1
e
L
M
MILLIMETERS
MIN
MAX
0.90
1.10
0.01
0.10
0.25
0.50
0.10
0.26
2.85
3.15
2.50
3.00
1.35
1.65
0.95 BSC
0.20
0.60
0_
10 _
RECOMMENDED
SOLDERING FOOTPRINT*
0.95
PITCH
2.40
5X
1.00
5X
0.70
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
9
MC74VHC1G09
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE M
D 5X
NOTE 5
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
0.10 T
M
2X
0.20 T
B
5
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
SIDE VIEW
C
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
MC74VHC1G09
PACKAGE DIMENSIONS
SOT−553, 5 LEAD
CASE 463B
ISSUE C
D
−X−
5
A
4
1
e
2
L
E
−Y−
3
b
HE
DIM
A
b
c
D
E
e
L
HE
c
5 PL
0.08 (0.003)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
M
X Y
MILLIMETERS
NOM
MAX
0.55
0.60
0.22
0.27
0.13
0.18
1.60
1.65
1.20
1.25
0.50 BSC
0.10
0.20
0.30
1.55
1.60
1.65
MIN
0.50
0.17
0.08
1.55
1.15
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.35
0.0531
1.0
0.0394
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.004
0.008
0.061
0.063
MIN
0.020
0.007
0.003
0.061
0.045
MAX
0.024
0.011
0.007
0.065
0.049
0.012
0.065
MC74VHC1G09
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
X
D
PIN ONE
INDICATOR
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
A
Y
4
HE
E
1
2 3
DIM
A
b
C
D
E
e
HE
L
L2
L3
C
TOP VIEW
SIDE VIEW
e
L
5X
5X
L3
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.175 REF
0.05
0.10
0.15
−−−
−−−
0.15
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
L2
5X
BOTTOM VIEW
b
PACKAGE
OUTLINE
0.08 X Y
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
12
MC74VHC1G09
PACKAGE DIMENSIONS
UDFN6, 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
A
B
D
L
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
L1
PIN ONE
REFERENCE
0.10 C
ÉÉÉ
ÉÉÉ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
0.10 C
DETAIL B
MOLD CMPD
DETAIL B
0.05 C
6X
DIM
A
A1
A2
b
D
E
e
L
L1
OPTIONAL
CONSTRUCTIONS
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.07 REF
0.20
0.30
1.45 BSC
1.00 BSC
0.50 BSC
0.30
0.40
−−−
0.15
MOUNTING FOOTPRINT
0.05 C
A1
SIDE VIEW
A2
e
6X
C
6X
SEATING
PLANE
L
1.24
3
1
DETAIL A
6X
0.53
6
0.30
PACKAGE
OUTLINE
4
BOTTOM VIEW
6X
0.50
PITCH
DIMENSIONS: MILLIMETERS
b
0.10 C A B
0.05 C
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
www.onsemi.com
13
MC74VHC1G09
PACKAGE DIMENSIONS
UDFN6, 1x1, 0.35P
CASE 517BX
ISSUE O
PIN ONE
REFERENCE
2X
0.08 C
2X
ÉÉÉ
ÉÉÉ
0.08 C
0.05 C
L1
A B
D
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
L3
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
ÉÉ
ÉÉ
ÇÇ
TOP VIEW
EXPOSED Cu
DETAIL B
A3
A1
MOLD CMPD
DETAIL B
A
ALTERNATE
CONSTRUCTION
0.05 C
SIDE VIEW
C
SEATING
PLANE
3
1
6X
MILLIMETERS
MIN
MAX
0.50
0.65
0.00
0.05
0.13 REF
0.17
0.23
1.00 BSC
1.00 BSC
0.35
0.20
0.40
−−−
0.15
0.26
0.33
RECOMMENDED
SOLDERING FOOTPRINT*
e
DETAIL A
DIM
A
A1
A3
b
D
E
e
L
L1
L3
L
6X
6X
0.25
0.52
1.20
6
4
BOTTOM VIEW
6X
PACKAGE
OUTLINE
b
0.07
M
C A B
0.05
M
C
1
0.35
PITCH
NOTE 3
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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