NLX1G125 Non-Inverting 3-State Buffer
The NLX1G125 is an advanced high−speed 2−input CMOS non−inverting 3−state buffer in ultra−small footprint. The NLX1G125 input structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage.
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5 PIN FLIP−CHIP CASE 499BG A1 XXXX A Y WW = Specific Device Code = Assembly Location = Year = Work Week XXXX AYWW
• • • • • • • •
High Speed: tPD = 2.7 ns (Typ) @ VCC = 5.0 V Designed for 1.65 V to 5.5 V VCC Operation Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C 24 mA Balanced Output Source and Sink Capability Balanced Propagation Delays Overvoltage Tolerant (OVT) Input Pins Ultra−Small Packages These are Pb−Free Devices
OE
1
5
VCC 1
PIN ASSIGNMENT
OE IN A GND OUT Y VCC 2 3 4 5
IN A
2
GND
3
4
OUT Y
Figure 1. Pinout (Top View) FUNCTION TABLE
A Input OE IN A L H X X = Don’t Care OE Input L L H Y Output L H Z
EN
OUT Y
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. P0
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Publication Order Number: NLX1G125/D
NLX1G125
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1) Power Dissipation in Still Air at 85°C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) VIN < GND VOUT < GND Parameter Value −0.5 to )7.0 −0.5 to )7.0 −0.5 to )7.0 −50 −50 $50 $100 ±100 −65 to )150 TBD TBD TBD TBD Level 1 UL 94 V−0 @ 0.125 in u2000 u200 N/A ±500 V Unit V V V mA mA mA mA mA °C °C °C °C/W mW
ILATCHUP
Latchup Performance Above VCC and Below GND at 125 °C (Note 5)
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA Dt/DV Positive DC Supply Voltage Digital Input Voltage (Note 6) Output Voltage Operating Free−Air Temperature Input Transition Rise or Fall Rate VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Parameter Operating Data Retention Only Min 1.65 1.5 0 0 −55 0 0 0 0 Max 5.5 5.5 5.5 5.5 +125 20 20 10 5.0 Unit V V V °C ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high or low−logic input voltage level.
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NLX1G125
DC ELECTRICAL CHARACTERISTICS
Symbol VIH Parameter Low−Level Input Voltage Low−Level Input Voltage High− Level Output Voltage VIN = VIH or VIL IOH = −100 mA VIN = VIH or VIL IOH = −4 mA IOH = −8 mA IOH = −12 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA VIN = VIH or VIL IOL = 100 mA VIN = VIH or VIL IOH = 4 mA IOH = 8 mA IOH = 12 mA IOH = 16 mA IOH = 24 mA IOH = 32 mA 0 v VIN v 5.5V Conditions VCC (V) 1.65 2.3 to 5.5 1.65 2.3 − 5.5 1.65 − 5.5 VCC−0.1 VCC TA = 25 5C Min 0.75 x VCC 0.70 x VCC 0.25 x VCC 0.30 x VCC VCC−0.1 Typ Max TA = −555C to +1255C Min 0.75 x VCC 0.70 x VCC 0.25 x VCC 0.30 x VCC V V Max Unit V
VIL
VOH
1.65 2.3 2.7 3.0 3.0 4.5 1.65 − 5.5
1.29 1.9 2.2 2.4 2.3 3.8
1.52 2.15 2.4 2.8 2.68 4.2 0.1
1.29 1.9 2.2 2.4 2.3 3.8 0.1 V
VOL
Low−Level Output Voltage
1.65 2.3 2.7 3.0 3.0 4.5 0 to 5.5
0.08 0.1 0.12 0.15 0.22 0.22
0.24 0.3 0.4 0.4 0.55 0.55 ±0.1
0.24 0.3 0.4 0.4 0.55 0.55 ±1.0 mA
IIN
Input Leakage Current 3−State Output Leakage Current Power−Off Output Leakage Current Quiescent Supply Current
IOZ
VIN = VIH or VIL 0vVOUTv5.5V
0
±0.5
±5.0
mA
IOFF
VIN = 5.5 V
0
1.0
10
mA
ICC
0 v VIN v VCC
5.5
1.0
10
mA
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NLX1G125
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 2.5 ns)
VCC (V) 1.65−1.95 2.3−2.7 3.0−3.6 Test Condition RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF 4.5−5.5 RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF tPZH, tPZL Output Enable Time (Figures 5, 6and 7, Table 1) 1.65−1.95 2.3−2.7 3.0−3.6 4.5−5.5 tPHZ, tPLZ Output Disable Time (Figures 5, 6and 7, Table 1) 1.65−1.95 2.3−2.7 3.0−3.6 4.5−5.5 CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (Note 7) 5.5 5.5 3.3 5.5 VIN = 0 V or VCC VIN = 0 V or VCC 10 MHz VIN = 0 V or VCC RL = R1 = 5−0 W, CL = 50 pF RL = 250 W, CL = 50 pF TA = 25 5C Min 2.0 1.0 0.8 1.2 0.5 0.8 2.0 1.8 1.2 0.8 2.0 1.5 0.8 0.3 2.5 2.5 9.0 11 8.0 Typ 6.0 3.4 2.5 3.1 1.8 2.3 7.6 Max 10 7.5 5.2 5.7 4.5 5.0 9.5 8.5 6.2 5.5 10 8.0 5.7 4.7 TA = −555C to +1255C Min 2.0 1.0 0.8 1.2 0.5 0.8 2.0 1.8 1.2 0.8 2.0 1.5 0.8 0.3 Max 10.5 8.0 5.5 6.0 4.8 5.3 10 9.0 6.5 5.8 10.5 8.5 6.0 5.0 pF pF pF ns ns Unit ns
Symbol tPLH, tPHL
Parameter Propagation Delay, Input to Output (Figures 3 and 4, Table 1)
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC.
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NLX1G125
tf = 3 ns
90% Vmi 10% 90% Vmi 10%
tf = 3 ns VCC INPUT GND
OE = GND OUTPUT CL * RL
INPUT A and B
tPHL
tPLH VOH
OUTPUT Y
Vmo
Vmo
VOL
*Includes all probe and jig capacitance. A 1 MHz square input wave is recommended for propagation delay tests.
Figure 3. Switching Waveform
2 INPUT VCC INPUT
Figure 4. TPLH or TPHL
R1 = 500 W OUTPUT CL = 50 pF RL = 500 W
VCC
OUTPUT CL = 50 pF RL = 250 W
A 1 MHz square input wave is recommended for propagation delay tests.
A 1 MHz square input wave is recommended for propagation delay tests.
Figure 5. TPZL or TPL
Figure 6. TPZH or TPHZ
2.7 V
OE tPZH On
Vmi tPHZ Vmo
Vmi 0V VCC VOH − 0.3 V ≈0V
tPZL On Vmo
tPLZ
≈ 3.0 V VOL + 0.3 V GND
Figure 7. AC Output Enable and Disable Waveform Table 1. OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VCC Symbol Vmi Vmo 3.3 V $ 0.3 V 1.5 V 1.5 V 2.7 V 1.5 V 1.5 V 2.5 V $ 0.2 V VCC/2 VCC/2
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NLX1G125
DEVICE ORDERING INFORMATION
Device NLX1G125FCT1G Package Flip−Chip 5 (Pb−Free) Shipping† 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NLX1G125
PACKAGE DIMENSIONS
5 PIN FLIP−CHIP CASE 499BG−01 ISSUE O
D AB
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A A1 b D E e MILLIMETERS MIN MAX 0.44 0.50 0.15 0.19 0.21 0.25 0.90 BSC 1.40 BSC 0.50 BSC
4X
0.10 C
0.10 C A 0.05 C SIDE VIEW e/2
5X
b
0.05 C A B 0.03 C
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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ÈÈ ÈÈ
e
C B A 1
PIN A1 REFERENCE
E
TOP VIEW A1
C
SEATING PLANE
SOLDERING FOOTPRINT*
0.50 PITCH 0.50 PITCH
A1
e e
5X
0.25
PACKAGE OUTLINE
2
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NL17SZ125/D