NM93C14N

General Description Features The NM93C13/C14 is 256/1024, respectively, bits of CMOS electrically erasable memory divided into 16/64 16-bit registers. They are fabricated using Fairchild Semiconductor’s floating-gate CMOS process for high speed, high reliability and low power. The NM93C13/C14 is available in an 8-pin SO package to save board space. The serial interface of the NM93C13/C14 is MICROWIRE™ compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions: Read, Erase/ Write Enable, Erase, Erase All, Write, Write All, and Erase/ Write Disable. All programming cycles are completely self-timed for simplified operation. The ready/busy status is available on the DO pin to indicate the completion of a programming cycle. n Typical active current 400 µA; Typical standby current 25 µA n Reliable CMOS floating gate technology n 4.5V to 5.5V operation in all modes n MICROWIRE compatible serial I/O n Self-timed programming cycle n Device status indication during programming mode n 15 years data retention n Endurance: 100,000 read/write cycles minimum n Packages available: 8-pin DIP, 8-pin SO Functional Diagram NM93C13/C14 NM93C13/C14 256-/1024-Bit Serial EEPROM NM93C13/C14 256-/1024-Bit Serial EEPROM March 1997 DS011291-1 © 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com DS011291 PrintDate=1997/07/28 PrintTime=12:26:12 10788 ds011291 Rev. No. 3 Proof 1 1 Connection Diagrams Dual-In-Line Package (N) and 8-Pin SO (M8) Alternate SO Pinout (TM8) NM93C14 Only DS011291-2 DS011291-3 Top View See Package NumberC8E and M08A Alternate SO Pinout (TM8) NM93C14 Only See Package M08A Ordering Information Pin Names Commercial Temp. Range (0˚C to +70˚C) Order Number* CS NM93C13N/NM93C14N SK Serial Data Clock NM93C13M8/NM93C14M8 DI Serial Data Input DO Serial Data Output NM93C14TM8 www.fairchildsemi.com Chip Select GND Ground VCC Power Supply 2 PrintDate=1997/07/28 PrintTime=12:26:13 10788 ds011291 Rev. No. 3 Proof 2 Absolute Maximum Ratings Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating Operating Conditions (Note 1) Ambient Operating Temperature NM93C13–NM93C14 Power Supply −65˚C to +150˚C +6.5V to −0.3V 0˚C to +70˚C 4.5V to 5.5V +300˚C 2000V DC and AC Electrical Characteristics (Note 2) VCC = 5.0V ± 10% (unless otherwise specified) ICC1 Symbol Operating Current Parameter ICC3 Standby Current IIL Input Leakage Conditions CS = VIH, SK = 1 MHz CS = 0V VIN = 0V to VCC Min Max Units 4 mA IOL Output Leakage VIN = 0V to VCC VIL Input Low Voltage VIH Input High Voltage 2 VCC + 1 VOL1 Output Low Voltage VOH1 Output High Voltage VOL2 Output Low Voltage 200 µA 10 µA −10 10 µA −0.1 0.8 V −10 IOL = 2.1 mA IOH = −400 µA 0.4 V 0.2 V 1 MHz 2.4 IOL = 10 µA IOH = −10 µA V VOH2 Output High Voltage fSK SK Clock Frequency tSKH SK High Time (Note 3) 300 ns tSKL SK Low Time (Note 3) 250 ns tSKS SK Setup Time 50 ns tCS Minimum CS Low Time 250 ns tCSS CS Setup Time 50 ns tDH D0 Hold Time 70 ns tDIS DI Setup Time 100 ns tCSH CS Hold Time 0 ns tDIH DI Hold Time 20 ns tPD1 Output Delay to “1” 500 ns tPD0 Output Delay to “0” 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in TRI-STATE ® 100 ns tWP Write Cycle Time 10 ms VCC − 0.2 CS = VIL Capacitance (Note 4) AC Test Conditions TA = 25˚C f = 1 MHz Symbol Test Output Load Typ Max Units COUT Output Capacitance 5 pF CIN Input Capacitance 5 pF 1 TTL Gate and CL = 100 pF Input Pulse Levels 0.4V to 2.4V Timing Measurement Reference Level Input 1V and 2V Output 0.8V and 2V Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: 100% functional test; AC/DC parameters sample tested to 0.4% AQL. Note 3: The SK frequency specification specifies a minimum SK clock period of 1 µs, therefore in an SK clock cycle tSKH + tSKL must be greater than or equal to 1 µs. For example, if the tSKL = 500 ns then the minimum tSKH = 500 ns in order to meet the SK frequency specification. Note 4: This parameter is periodically sampled and not 100% tested. 3 PrintDate=1997/07/28 PrintTime=12:26:16 10788 ds011291 Rev. No. 3 www.fairchildsemi.com Proof 3 Functional Description put on the data-in (DI) pin, CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). DO = logical 0 indicates that programming is still in progress. DO = logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. Erase All (ERAL): The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical “1” state. The Erase All cycle is identical to the ERASE cycle except for the different op-code. As in the ERASE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). The ERASE ALL instruction is not required, see (Note 5) . Write All (WRAL): The NM93C13/C14 have 7 instructions as described below. Note that the MSB of any instruction is a “1” and is viewed as a start bit in the interface sequence. For the C13 and C14 the next 8 bits carry the op code and the 6-bit address for register selection. Read (READ): The READ instruction outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. Erase/Write Enable (EWEN): When VCC is applied to the part, it powers up in the Erase/ Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC is removed from the part. Erase (ERASE): The ERASE instruction will program all bits in the specified register to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). DO = logical “0” indicates that programming is still in progress. DO = logical “1” indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. Write (WRITE): The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is The WRAL instruction will simultaneously program all registers with the data pattern specified in the instruction. As in the WRITE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). Erase/Write Disable (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. Note 5: The NM93C13/C14 devices do not require an “ERASE” or “ERASE ALL” prior to the “WRITE” and “WRITE ALL” instructions. The “ERASE” and “ERASE ALL” instructions are included to maintain compatibility with the NMOS NMC9346. Instruction Set for the NM93C13 and NM93C14 SB Op Code Address READ Instruction 1 10 A5–A0 Reads data stored in memory at specified address. EWEN 1 00 11XXXX Write enable must precede all programming modes. ERASE 1 11 A5–A0 WRITE 1 01 A5–A0 ERAL 1 00 10XXXX WRAL 1 00 01XXXX EWDS 1 00 00XXXX www.fairchildsemi.com Data Comments Erase selected register. D15–D0 Writes selected register. Erases all registers. D15–D0 Writes all registers. Disables all programming instructions. 4 PrintDate=1997/07/28 PrintTime=12:26:19 10788 ds011291 Rev. No. 3 Proof 4 Timing Diagrams Synchronous Data Timing DS011291-4 READ: DS011291-5 *Address bits A5 and A4 become “don’t care” for NM93C13. EWEN: DS011291-6 *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. 5 PrintDate=1997/07/28 PrintTime=12:26:20 10788 ds011291 Rev. No. 3 www.fairchildsemi.com Proof 5 Timing Diagrams (Continued) EWDS: DS011291-7 *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. WRITE: DS011291-8 *Address bit A5 and A4 become “don’t care” for NM93C13. WRAL: DS011291-9 *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. www.fairchildsemi.com 6 PrintDate=1997/07/28 PrintTime=12:26:20 10788 ds011291 Rev. No. 3 Proof 6 Timing Diagrams (Continued) ERASE: DS011291-10 *Address bits A5 and A4 are “don’t care” for NM93C13. ERAL: DS011291-11 Book Extract End 7 PrintDate=1997/07/28 PrintTime=12:26:21 10788 ds011291 Rev. No. 3 www.fairchildsemi.com Proof 7 THIS PAGE IS IGNORED IN THE DATABOOK 8 PrintDate=1997/07/28 PrintTime=12:26:21 10788 ds011291 Rev. No. 3 Proof 8 Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Out-Line Package (M8) Order Number NM93C13M8 or NM93C14M8 Package Number M08A Molded Dual-In-Line Package (N) Order Number NM93C13N or NM93C14N Package Number N08E 9 PrintDate=1997/07/28 PrintTime=12:26:21 10788 ds011291 Rev. No. 3 www.fairchildsemi.com Proof 9 9 NM93C13/C14 256-/1024-Bit Serial EEPROM LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.fairchildsemi.com Fairchild Europe Fax: Email: Deutsch Tel: English Tel: Français Tel: Italiano Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 1 80-530 85 85 +49 (0) 1 80-532 78 32 +49 (0) 1 80-532 93 58 +49 (0) 1 80-534 16 80 Fairchild Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. PrintDate=1997/07/28 PrintTime=12:26:21 10788 ds011291 Rev. No. 3 Proof 10