NM93C56
2048-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
Features
NM93C56 is a 2048-bit CMOS non-volatile EEPROM organized
as 128 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the NM93C56 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
■ Wide VCC 2.7V - 5.5V
“LZ” and “L” versions of NM93C56 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space considerations.
■ Endurance: 1,000,000 data changes
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ No Erase instruction required before Write instruction
■ Self timed write cycle
■ Device status during programming cycles
■ 40 year data retention
■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
VCC
CS
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
SK
DI
INSTRUCTION
REGISTER
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
ADDRESS
REGISTER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
VSS
16
DATA IN/OUT REGISTER
16 BITS
DO
© 2000 Fairchild Semiconductor International
NM93C56 Rev. E
DATA OUT BUFFER
1
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
February 2000
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
1
8
VCC
SK
2
7
NC
DI
3
6
NC
DO
4
5
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
NC
No Connect
VCC
Power Supply
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Ordering Information
NM
93
C
XX
LZ
E
XXX
Letter Description
Package
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined)
WRITE ENABLE CYCLE (WEN)
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A7
A6
A1
A0
Address
Bits(8)
High - Z
DO
93C56:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
8
NM93C56 Rev. E
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NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Timing Diagrams (Continued)
WRITE DISABLE CYCLE (WDS)
tCS
CS
SK
DI
1
0
Star t
Bit
0
A7
A6
Opcode
Bits(2)
A1
A0
Address
Bits(8)
High - Z
DO
93C56:
A d d r e s s b i t s p a t t e r n - > 0 - 0 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE CYCLE (WRITE)
tCS
CS
SK
DI
1
0
Star t
Bit
1
A7
A6
Opcode
Bits(2)
A1
A0
D15 D14
Address
Bits(8)
D1
D0
tWP
Data
Bits(16)
High - Z
DO
Ready
Busy
93C56:
Address bits patter n -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined)
Data bits patter n
-> User defined
WRITE ALL CYCLE (WRALL)
tCS
CS
SK
DI
1
Star t
Bit
0
0
Opcode
Bits(2)
A7
A6
A1
A0
D15 D14
Address
Bits(8)
Data
Bits(16)
D1
D0
tWP
High - Z
DO
Ready
Busy
93C56:
A d d r e s s b i t s p a t t e r n - > 0 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
Data bits pattern
-> User defined
9
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Timing Diagrams (Continued)
ERASE CYCLE (ERASE)
tCS
CS
SK
1
DI
Star t
Bit
1
1
Opcode
Bits(2)
DO
A7
A6
A1
A0
tWP
Address
Bits(8)
High - Z
Ready
Busy
93C56:
Address bits pattern -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined)
ERASE ALL CYCLE (ERAL)
tCS
CS
SK
1
DI
Star t
Bit
1
1
Opcode
Bits(2)
DO
A7
High - Z
A6
A1
A0
tWP
Address
Bits(8)
Ready
Busy
93C56:
Address bits patter n -> 1-0-x-x-x-x-x-x ; (x -> Don't Care, can be 0 or 1)
CLEARING READY STATUS
CS
SK
DI
Star t
Bit
DO
High - Z
Ready
High - Z
Busy
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued (instead of getting ter minated, as shown) as if a new
instr uction is being issued.
10
NM93C56 Rev. E
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NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
11
NM93C56 Rev. E
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0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
12
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
+
Pin #1 IDENT
8
0.032 ± 0.005
(6.35 ± 0.127)
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
(0.813 ± 0.127)
RAD
5
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fax:
+44 (0) 1793-856858
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Tel:
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
13
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
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