NOII4SM6600A-QDC

DATA SHEET www.onsemi.com 6.6 Megapixel CMOS Image Sensor NOII4SM6600A Features • • • • • • • • • • • • • • 2210 (H) x 3002 (V) Active Pixels 3.5 mm x 3.5 mm Square Pixels 1 inch Optical Format Monochrome Output Frame Rate: ♦ 5 fps for Active Window of 2210 x 3002 ♦ 89 fps for Active Window of 640 x 480 High Dynamic Range Modes: Double Slope, Non Destructive Read out (NDR) Electronic Rolling Shutter Master Clock: 40 MHz Single 2.5 V Supply 3.3 V Supply for Extended Dynamic Range −30°C to +65°C Operational Temperature Range 68-Pin LCC Package Power Dissipation: 225 mW These Devices are Pb−Free and are RoHS Compliant Figure 1. IBIS4−6600 Image Sensor Applications • Machine Vision • Biometry • Document Scanning Description The IBIS4-6600 is a solid-state CMOS image sensor that integrates complete analog image acquisition, and a digitizer and digital signal processing system on a single chip. This image sensor has a resolution of 6.6 MPixel with 2210 x 3002 active pixels. The image size is fully programmable for user-defined windows. The pixels are on a 3.5 mm pitch. The user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digital zoom. Subsampling reduces resolution while maintaining the constant field of view. The analog video output of the pixel array is processed by an on-chip analog signal pipeline. Double Sampling (DS) eliminates the fixed pattern noise. The programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit ADC converts the analog data to a 10-bit digital word stream. The sensor uses a three-wire Serial-Parallel (SPI) interface. It operates with a single 2.5 V power supply and requires only one master clock for operation up to 40 MHz. It is housed in a 68-pin ceramic LCC package. This data sheet enables the development of a camera system, based on the described timing and interfacing given in the following sections. ORDERING INFORMATION Marketing Part Number NOII4SM6600A-QDC Description Mono with Glass Package 68 pin LCC NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. © Semiconductor Components Industries, LLC, 2014 August, 2021 − Rev. 16 1 Publication Order Number: NOII4SM6600A/D NOII4SM6600A SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Specification Pixel Architecture 3T-Pixel Pixel Size 3.5 mm x 3.5 mm Resolution 2210 x 3002 Pixel Rate 40 MHz Shutter Type Electronic Rolling Shutter Full Frame Rate 5 frames/second Remarks The resolution and pixel size results in a 7.74 mm x 10.51 mm optical active area. Using a 40 MHz system clock and 1 or 2 parallel outputs Increases with ROI read out and/or subsampling ELECTRO OPTICAL SPECIFICATIONS Parameter Specification Remarks FPN (local) 7.5 ns • THOLD > 7.5 ns There are 3 control signals that operate the image sensor: SYS_CLOCK Y_CLOCK Y_START It is important that these signals are free of any glitches. Figure 17. Relative Timing of the Three Control Signals Basic Frame and Line Timing The pulse width of Y_CLOCK must be a minimum of one clock cycle and three clock cycles for Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state. The basic frame and line timing of the IBIS4-6600 sensor is shown in Figure 18. T1 Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel reset levels, and start the readout of one line. It depends on the granularity of the X-sequencer clock (see Table 13 on page 20). T2 Pixels counted by pixel counter until the value of Nrof_pixels register is reached. Pixel_valid goes high when the internal X_sync signal is generated. In other words, when the readout of the pixels is started. Pixel_valid goes low when the pixel counter reaches the value loaded in the Nrof_pixels register. Eol goes high Sys_clock cycle after the falling edge of Pixel_valid. T3 EOF goes high when the line counter reaches the value loaded in the NROF_LINES register and the line is read (PIXEL_VALID goes low). T4 The time delay between successive Y_CLOCK pulses needs to be equal to avoid any horizontal illumination (integration) discrepancies in the image. Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals are delayed with at least 2 SYS_CLOCK periods to let the sensor run automatically. It must however be noted that on power-on, the FIRST Y_START and Y_CLOCK must be generated by the external system. Figure 18. Basic Frame and Line Timing www.onsemi.com 22 NOII4SM6600A Pixel Output Timing Using Two Analog Outputs Figure 19. Pixel Output Timing using Two Analog Outputs The pixel signal at the OUT1 (OUT2) output becomes valid after four SYS_CLOCK cycles when the internal X_SYNC (equal to start of PIXEL_VALID output) appears (see Figure 19). The PIXEL_VALID and EOL/EOF pulses can be delayed by the user through the DELAY register. T1: Row blanking time (see Table 13 on page 20) T2: 4 SYS_CLOCK cycles. Multiplexing to One Analog Output The pixel signal at the OUT1 output becomes valid after five SYS_CLOCK cycles when the internal X_SYNC (equal to start of PIXEL_VALID output) appears (see Figure 20). The PIXEL_VALID and EOL/EOF pulses can be delayed by the user through the DELAY register. T1: Row blanking time T2: 5 SYS_CLOCK cycles. Figure 20. Pixel Output Timing Multiplexing to One Analog Output www.onsemi.com 23 NOII4SM6600A ADC Timing Two Analog Outputs Figure 21 shows the timing of the ADC using two analog outputs. Internally, the ADCs sample on the falling edge of the ADC_CLOCK (in case of internal clock, the clock is half the SYS_CLOCK). T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total pipeline delay of four pixels. Figure 21. ADC Timing using Two Analog Outputs One Analog Output Figure 22 shows the timing of the ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK. T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles. Figure 22. ADC Timing using One Analog Output www.onsemi.com 24 NOII4SM6600A PACKAGE INFORMATION Pin List Description The following table lists all the pins and their functions. There are a total of 68 pins. All pins with the same name can be connected together. Table 16. PIN LIST Pin Pin Name Pin Type Expected Voltage [V] Pin Description 1 CMD_COL_CTU Input 0 Biasing of columns (ctu). Decouple with 100 nF to GNDA. 2 CMD_COL Input 1.08 Biasing of columns. Connect to VDDA with R = 10 kW and decouple to GNDA with C = 100 nF. 3 CMD_COLAMP Input 0.66 Biasing of column amplifiers. Connect to VDDA with R = 100 kW and decouple to GNDA with C = 100 nF. 4 CMD_COLAMP_CTU Input 0.37 Biasing of column amplifiers. Connect to VDDA with R = 10 MW and decouple to GNDA with C = 100 nF. 5 RCAL_DAC_DARK Input 1.27 at code 128 DAC_DARK reg Biasing of DAC for dark reference. Can be used to set output range of DAC. Default: Decouple to GNDA with C = 100 nF 6 RCAL_DAC_OUT Input 0 Biasing of DAC for output dark level. Can be used to set output range of DAC. Default: Connect to GNDA 7 VDDA Power 2.5 VDD of analog part [2.5 V] 8 GNDA Power 0 GND (&substrate) of analog part 9 VDDD Power 2.5 VDD of digital part [2.5 V] 10 GNDD Power 0 GND (&substrate) of digital part 11 CMD_OUT_1 Input 0.78 Biasing of first stage output amplifiers. Connect to VDDAMP with R = 50 kW and decouple to GNDAMP with C = 100 nF. 12 CMD_OUT_2 Input 0.97 Biasing of second stage output amplifiers. Connect to VDDAMP with R = 25 kW and decouple to GNDAMP with C = 100 nF. 13 CMD_OUT_3 Input 0.67 Biasing of third stage output amplifiers. Connect to VDDAMP with R = 100 kW and decouple to GNDAMP with C = 100 nF. 14 SPI_CLK Input - Clock of digital parameter upload. Shifts on rising edge. 15 SPI_DATA Input - Serial address and data input. 16-bit word. Address first. MSB first. 16 VDDAMP Power 2.5 VDD of analog output [2.5 V] (Can be connected to VDDA) 17 CMD_FS_ADC Input 0.73 Biasing of first stage ADC. Connect to VDDA_ADC with R = 50 kW and decouple to GNDA_ADC with C = 100 nF. 18 CMD_SS_ADC Input 0.73 Biasing of second stage ADC. Connect to VDDA_ADC with R = 50 kW and decouple to GNDA_ADC. 19 CMD_AMP_ADC input 0.59 Biasing of input stage ADC. Connect to VDDA_ADC with R = 180 kW and decouple to GNDA_ADC with C = 100 nF. 20 GNDAMP Ground 0 GND (&substrate) of analog output 21 OUT1 Output Black level: 1 at code 190 DAC_RAW register Analog output 1 22 ADC_IN1 Input See OUT1. Analog input ADC 1 23 VDDAMP Power 2.5 VDD of analog output [2.5 V] (Can be connected to VDDA) 24 OUT2 Output Black level: 1 at code 190 DAC_RAW register Analog output 2 25 ADC_IN2 See OUT2. Analog input ADC 2 26 VDDD Power 2.5 VDD of digital part [2.5 V] 27 GNDD Power 0 GND (&substrate) of digital part 28 GNDA Power 0 GND (&substrate) of analog part Input www.onsemi.com 25 NOII4SM6600A Table 16. PIN LIST Pin Pin Name 29 VDDA 30 REG_CLOCK 31 Pin Type Power Expected Voltage [V] Pin Description 2.5 VDD of analog part [2.5 V] Input - Register clock. Data on internal bus is copied to corresponding registers on rising edge. SYS_CLOCK Input - System clock defining the pixel rate (nominal 40 MHz, 50% ± 5% duty cycle) 32 SYS_RESET Input - Global system reset (active high) 33 Y_CLK Input - Line clock 34 Y_START Input - Start frame readout 35 GNDD_ADC Power 0 GND (&substrate) of digital part ADC 36 VDDD_ADC Power 2.5 VDD of digital part [2.5 V] ADC 37 GNDA_ADC Power 0 GND (&substrate) of analog part 38 VDDA_ADC Power 2.5 VDD of analog part [2.5 V] 39 VHIGH_ADC Input 1.5 ADC high reference voltage (for example, connect to VDDA_ADC with R = 560 W and decouple to GNDA_ADC with C = 100 nF) 40 VLOW_ADC Input 0.42 ADC low reference voltage (for example, connect to GNDA_ADC with R = 220 W and decouple to GNDA_ADC with C = 100 nF) 41 GNDA_ADC Power 0 GND (&substrate) of analog part 42 VDDA_ADC Power 2.5 VDD of analog part [2.5 V] 43 GNDD_ADC Power 0 GND (&substrate) of digital part ADC 44 VDDD_ADC Power 2.5 VDD of digital part [2.5 V] ADC 45 VDD_RESET_DS Power 46 ADC_CLK_EXT 47 2.5 (for no dual slope) Variable reset voltage (dual slope) Input - External ADC clock EOL Output - Diagnostic end of line signal (produced by sequencer), can be used as Y_CLK 48 EOF Output - Diagnostic end of frame signal (produced by sequencer), can be used as Y_START 49 PIX_VALID Output - Diagnostic signal. High during pixel readout 50 TEMP Output - Temperature measurement. Output voltage varies linearly with temperature. 51 ADC_D Output - ADC data output (MSB) 52 VDD_PIX Power 2.5 VDD of pixel core [2.5 V] 53 GND_AB Power 0 Anti-blooming ground. Set to 1 V for improved anti-blooming behavior 54 ADC_D Output - ADC data output 55 ADC_D Output - ADC data output 56 ADC_D Output - ADC data output 57 ADC_D Output - ADC data output 58 ADC_D Output - ADC data output 59 ADC_D Output - ADC data output 60 VDD_RESET Power 2.5 Reset voltage [2.5 V]. Highest voltage to the chip. 3.3 V for extended dynamic range or ‘hard reset’. 61 ADC_D Output - ADC data output 62 ADC_D Output - ADC data output 63 ADC_D Output - ADC data output (LSB) www.onsemi.com 26 NOII4SM6600A Table 16. PIN LIST Pin Pin Name Pin Type Expected Voltage [V] Pin Description 64 BS_RESET Input - Boundary scan (allows debugging of internal nodes): Reset. Tie to GND if not used. 65 BS_CLOCK Input - Boundary scan (allows debugging of internal nodes): Clock. Tie to GND if not used. 66 BS_DIN Input - Boundary scan (allows debugging of internal nodes): In. Tie to GND if not used. 67 BS_BUS Output - Boundary scan (allows debugging of internal nodes): Bus. Leave floating if not used. 68 CMD_DEC 0.74 Biasing of X and Y decoder. Connect to VDDD with R = 50 kW and decouple to GNDD with C = 100 nF. Input Y_START and Y_CLOCK pulse. Before this X_SYNC, the chip may draw more current from the analog power supply VDDA. It is therefore favorable to have separate analog and digital supplies. The current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting the resistor on pin 3 (CMD_COLAMP) at startup. Note on Power On Behavior At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0). The X-shift registers are in a defined state after the first X_SYNC, which occurs a few microseconds after the first www.onsemi.com 27 NOII4SM6600A MECHANICAL SPECIFICATIONS Table 17. MECHANICAL SPECIFICATIONS Parameters Die (with Pin 1 to the left center) Description Min Die thickness Die Size Max Units 0.74 mm 9120.1 x 11960.1 mm Die center, X offset to the center of package (–50) 0 (+50) mm Die center, Y offset to the center of the package (–50) 0 (+50) mm Die position, X tilt −1 0 1 deg Die position, Y tilt −1 0 1 deg Die placement accuracy in package Die rotation accuracy Glass Lid Typ (–50) (+50) mm –1 1 deg Optical center referenced from package center (X−dir) (–50) −155.58 (+50) mm Optical center referenced from package center (Y−dir) (–50) 446.95 (+50) mm Pixel (0,0) referenced from package center (x−dir) (–50) −4023 (+50) mm Pixel (0,0) referenced from package center (y−dir) (–50) −4806 (+50) mm Distance from PCB plane to top of the die surface 1.562 mm Distance from the top of the die surface to the top of the glass lid 2.048 mm 19.5 x 17.5 mm 1 mm Dimensions Thickness Spectral range for window 400 1000 nm Transmission of the glass lid 92 % Mechanical shock JESD22-B104C; Condition G 200 G Vibration JESD22-B103B; Condition 1 2000 Hz Mounting profile Lead−free profile for LCC package if no socket is used 20 www.onsemi.com 28 NOII4SM6600A Glass Lid The IBIS4-6600 image sensor uses a glass lid without any coatings. Figure 24 shows the transmission characteristics of the glass lid. As shown in Figure 24, no infrared attenuating filter glass is used. (source: http://www.pgo−online.com). Figure 23. Transmission Characteristics of the Glass Lid ADDITIONAL REFERENCES AND RESOURCES For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions document from www.onsemi.com. For information on Return Material Authorization procedures, please refer to the RMA Policy Procedure document from www.onsemi.com. The Product Acceptance Criteria document, which lists criteria to which this device is tested prior to shipment, is available upon request. Application Notes and other resources can be found linked to the product web page at www.onsemi.com. Additional information on this device may also be available in the Image Sensor Portal, accessible within the MyON section of www.onsemi.com. A signed NDA is required to access the Image Sensor Portal – please see your onsemi sales representative for more information. For information on ESD and cover glass care and cleanliness, please download the Application Note Image Sensor Handling and Best Practices (AN52561/D) from www.onsemi.com. www.onsemi.com 29 NOII4SM6600A ACRONYMS Acronym Description Acronym Description ADC analog-to-digital converter IP intellectual property AFE analog front end LE line end BL black pixel data LS line start CDM Charged Device Model LSB least significant bit CDS correlated double sampling LVDS low-voltage differential signaling CMOS complementary metal oxide semiconductor MBS mixed boundary scan CRC cyclic redundancy check MSB most significant bit DAC digital-to-analog converter PGA programmable gain amplifier DDR double data rate PLS parasitic light sensitivity DFT design for test PRBS pseudo-random binary sequence DNL differential nonlinearity PRNU pixel random non-uniformity DS Double Sampling QE quantum efficiency DSNU dark signal non-uniformity RGB red green blue EIA Electronic Industries Alliance RMA Return Material Authorization ESD electrostatic discharge RMS root mean square FE frame end ROI region of interest FF fill factor ROT row overhead time FOT frame overhead time S/H sample and hold FPGA Field Programmable Gate Array SNR signal-to-noise ratio FPN fixed pattern noise SPI serial peripheral interface FPS frames per second TBD to be determined FS frame start TIA Telecommunications Industry Association HBM Human Body Model TJ Junction Temperature IMG regular pixel data TR training pattern INL integral nonlinearity % RH Percent Relative Humidity www.onsemi.com 30 NOII4SM6600A GLOSSARY conversion gain A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. Conversion gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance of the photodiode or sense node. CDS Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. DNL Differential nonlinearity (for ADCs) DSNU Dark signal non-uniformity. This parameter characterizes the degree of non-uniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the actual QE of a pixel divided by the QE of a photodiode of equal area. In practice, it is never measured. INL Integral nonlinearity (for ADCs) IR Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm. Lux Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m2 = 1/683 W/m2) pixel noise Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units Units for light measurement that take into account human physiology. PLS Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes. PRNU Photo-response non-uniformity. This parameter characterizes the spread in response of pixels, which is a source of FPN under illumination. QE Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. It is photon wavelength and pixel color dependent. read noise Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset The process by which a pixel photodiode or sense node is cleared of electrons. “Soft” reset occurs when the reset transistor is operated below the threshold. “Hard” reset occurs when the reset transistor is operated above threshold. reset noise Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel designs, reset noise can be removed with CDS. responsivity The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units are typically A/W and are dependent on the incident light wavelength. Note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. ROI Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. The ROI can be the entire array or a small subsection; it can be confined to a single color plane. sense node In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodiode itself. sensitivity A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts upon illumination with light. Units are typically V/(W/m2)/sec and are dependent on the incident light wavelength. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683 lux is equal to 1 W/m2; the units of sensitivity are quoted in V/lux/sec. Note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response The photon wavelength dependence of sensitivity or responsivity. SNR Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum up to half the Nyquist frequency. temporal noise Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels. www.onsemi.com 31 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LCC68, 24.13x24.13 CASE 115AQ ISSUE A DATE 01 DEC 2011 GENERIC MARKING DIAGRAM XXXXX A WL YY WW NNNN DOCUMENT NUMBER: DESCRIPTION: 98AON56540E LCC68, 24.13 X 24.13 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Serial Number Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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